2 current and voltage dc offset register ( i, 3 current and voltage gain register ( i, Cs5463 – Cirrus Logic CS5463 User Manual

Page 27: 4 cycle count register ( cycle count ), 5 pulseratee register ( pulseratee )

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CS5463

DS678F3

27

6.1.2 Current and Voltage DC Offset Register ( I

DCoff

, V

DCoff

)

Address: 1 (Current DC Offset); 3 (Voltage DC Offset)

Default = 0x000000

The DC Offset registers (I

DCoff

,V

DCoff

)

are initialized to 0.0 on reset. When DC Offset calibration is performed, the

register is updated with the DC offset measured over a computation cycle. DRDY will be set at the end of the
calibration. This register may be read and stored for future system offset compensation. The value is represent-
ed in two's complement notation and in the range of -1.0

 I

DCoff

, V

DCoff

 1.0, with the binary point to the right of

the MSB. See Section 7.1.2.1

DC Offset Calibration Sequence

on page 37 for more information.

6.1.3 Current and Voltage Gain Register ( I

gn

, V

gn

)

Address: 2 (Current Gain); 4 (Voltage Gain)

Default = 0x400000 = 1.000

The gain registers (I

gn

,V

gn

)

are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,

the register is updated with the gain measured over a computation cycle. DRDY will be set at the end of the
calibration. This register may be read and stored for future system gain compensation. The value is in the range
0.0

 I

gn

,V

gn

< 3.9999, with the binary point to the right of the second MSB.

6.1.4 Cycle Count Register ( Cycle Count )

Address: 5

Default = 0x000FA0 = 4000

Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024

N). A one second computational cycle period occurs when

MCLK = 4.096 MHz, K = 1, and N = 4000.

6.1.5 PulseRateE Register ( PulseRateE )

Address: 6

Default = 0x800000 = 1.00 (2 kHz @ 4.096 MHz MCLK)

PulseRateE sets the frequency of E1, E2, & E3

pulses. E1, E2, E3 frequency = (MCLK x PulseRateE) / 2048 at

full scale. For a 4 khz sample rate, the maximum pulse rate is 2 khz. The value is represented in two's comple-
ment notation and in the range is -1.0

 PulseRateE  1.0, with the binary point to the right of the MSB. Negative

values have the same effect as positive. See Section 5.5

Energy Pulse Output

on page 17 for more information.

MSB

LSB

-(2

0

)

2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

2

-7

.....

2

-17

2

-18

2

-19

2

-20

2

-21

2

-22

2

-23

MSB

LSB

2

1

2

0

2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

.....

2

-16

2

-17

2

-18

2

-19

2

-20

2

-21

2

-22

MSB

LSB

2

23

2

22

2

21

2

20

2

19

2

18

2

17

2

16

.....

2

6

2

5

2

4

2

3

2

2

2

1

2

0

MSB

LSB

-(2

0

)

2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

2

-7

.....

2

-17

2

-18

2

-19

2

-20

2

-21

2

-22

2

-23

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