Cirrus Logic CS6422 - Manual (Page 25)

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3.7.1 AERLE - AEC ERLE THRESHOLD
The CS6422 will allow full-duplex operation when the ERLE provided by the AEC exceeds the value
programmed at AErle. See also AFNse. See Section 6., “Glossary” for a definition of ERLE.
3.7.2 AFNSE - AEC FULL-DUPLEX NOISE THRESHOLD
AFNse works in conjunction with AErle to determine when the CS6422 should transition into full-du-
plex operation. AFNse specifies a noise level. If the current noise level at the near-end input is greater
than AFNse, then AErle is used to determine if full-duplex is allowed, that is, the AEC must provide
at least AErle of cancellation in order for the CS6422 to transition to full-duplex.
If the noise level is below AFNse, the CS6422 uses an internal estimate of asymptotic performance
to determine whether or not to transition to full-duplex. If AFNse is zero, AErle is used as the exclusive
full-duplex criterion.
3.7.3 NERLE - NEC ERLE THRESHOLD
The CS6422 will allow full-duplex operation only when the ERLE provided by the NEC exceeds the
threshold set by NErle. See also NFNse. See Section 6., “Glossary” for a definition of ERLE.
3.7.4 NFNSE - NEC FULL-DUPLEX NOISE THRESHOLD
NFNse works in conjunction with NErle to determine when the CS6422 should transition into full-du-
plex operation. If the noise level at the far-end input is greater than NFNse, then NErle is used to de-
termine if full-duplex is allowed. If the noise level is below the level of NFNse, the CS6422 uses an
internal estimate of asymptotic performance to determine whether or not to transition to full-duplex. If
NFNse is zero, NErle is always used as the exclusive full-duplex criterion.
If NFNse is non-zero, then the CS6422 will automatically disable the NEC if a network coupling path
is not detected. Thus in systems in which the presence of a network path is not known, NFNse should
be set to a non-zero value. See also AuNECD.
3.7.5 RGAIN - RECEIVE ANALOG GAIN
RGain selects the amount of additional on-chip analog gain to be supplied to the network input of the
CS6422. The output of this amplifier stage feeds the receive path ADC, and can supply 0 dB, 6 dB,
9.5 dB, or 12 dB of gain to the signal path. The gain setting defaults to 0 dB.
Note: Changing the analog gain will change the full-scale voltage as applied to the input pin. Make
sure that the ADC input does not clip with the gain stage on.3.
3.7.6 TGAIN - TRANSMIT ANALOG GAIN
TGain selects the amount of additional on-chip analog gain to be supplied to the acoustic input of the
CS6422. The output of this amplifier stage feeds the transmit path ADC, and can supply 0 dB, 6 dB,
9.5 dB, or 12 dB of gain to the signal path. The gain setting defaults to 0 dB.
Note: Changing the analog gain will change the full-scale voltage as applied to the input pin. Make
sure that the ADC input does not clip with the gain stage on.
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