Cirrus Logic CS8420 - Manual (Page 15)

DS245F4 15
CS8420
The AESBP switch allows a TTL level, bi-phase mark-encoded data stream connected to RXP to be routed to the
TXP and TXN pin drivers. The TXOFF switch causes the TXP and TXN outputs to be driven to ground
In modes including the SRC function, there are two audio-data-related clock domains. One domain includes the in-
put side of SRC, plus the attached data source. The second domain includes the output side of the SRC, plus any
attached output ports.
There are two possible clock sources. The first known as the recovered clock, is the output of a PLL, and is con-
nected to the RCMK pin. The input to the PLL can be either the incoming AES3 data stream or the ILRCK word rate
clock from the serial audio input port. The second clock is input via the OMCK pin, and would normally be a crystal-
derived stable clock. The Clock Source Control Register bits determine which clock is connected to which domain.
By studying the following drawings, and appropriately setting the Data Flow Control and Clock Source Control reg-
ister bits, the CS8420 can be configured to fit a variety of application requirements.
The following drawings illustrate the possible valid data flows. The audio data flow is indicated by the thin lines; the
clock routing is indicated by the bold lines. The register settings for the Data Flow Control register and the Clock
Source Register are also shown for each data flow. Some of the register settings may appear to be not relevant to
the particular data flow in question, but have been assigned a particular state. This is done to minimize power con-
sumption. The AESBP data path from the RXP pin to the AES3 output drivers, and the TXOFF control, have been
omitted for clarity, but are present and functional in all modes where the AES3 transmitter is in use.
Figures 8 and 9 show audio data entering via the serial audio input port, then passing through the sample rate con-
verter, and then output both to the serial audio output port and to the AES3 transmitter. Figure 8 shows the PLL
recovering the input clock from ILRCK word clock. Figure 9 shows using a direct 256*Fsi clock input via the RMCK
pin, instead of the PLL.
Figure 10 shows audio data entering via the AES3 Receiver. The PLL locks onto the pre-ambles in the incoming
audio stream, and generates a 256*Fsi clock. The rate-converted data is then output via the serial audio output port
and via the AES3 transmitter.
Figure 11 shows the same data flow as Figure 8 . The input clock is derived from an incoming AES3 data stream.
The incoming data must be synchronous to the AES3 data stream.
Figure 12 shows the same data flow as Figure 8 . The input data must be synchronous to OMCK. The output data
is clocked by the recovered PLL clock from an AES3 input stream. This may be used to implement a “house sync”
architecture.
Figure 8 shows audio data entering via the AES3 receiver, passing through the sample rate converter, and then ex-
iting via the serial audio output port. Synchronous audio data may then be input via the serial audio input port and
output via the AES3 transmitter.
Figure 14 is the same as Figure 13 , but without the sample rate converter. The whole data path is clocked via the
PLL generated recovered clock.
Figure 15 illustrates a standard AES3 receiver function, with no rate conversion.
Figure 16 shows a standard AES3 transmitter function, with no rate conversion.