Cirrus Logic AN364 - Manual (Page 19)

AN364
AN364REV3 19
excess charge from capacitor C4 by turning ‘ON’ transistor Q3, dissipating the power into load resistors R6
and R16. The clamp load resistors R6 and R16 must each be 2k
 2W resistors for 230V and 500 2W
resistors for 120V systems.
Step 25) Designing the EMI Filter
The switching frequency of the CS1610/11 can cause resonance in the EMI filter, so it is important to carefully
design it. Resonance can cause undue noise, oscillation, and impact power factor. The resonant frequencies
on the LC filters must be less than 1/10 of the minimum switching frequency of the boost stage. There is a
variety of dimmers, and each behaves differently. All dimmers are sensitive to the presence of EMI filters with
large capacitance or inductance. Capacitance on the AC side of the rectifier should be avoided. Capacitance
to the immediate output of the rectifier bridge should be minimized for optimal dimmer compatibility.
The EMI filter and the reactances associated with the dimmer constitute a complex reactive network that has
minimal damping. This reactive network will ring as it is excited by the dimmer turn on and the boost stage
conduction. Should the current in the dimmer's TRIAC reverse, the TRIAC will open, disturbing the dimmer
timing, which results in flicker. For this reason limitations are imposed on the values assigned to the EMI
components.
Step 26) Layout
Basics for any power layout:
• Keep power traces as short as possible.
• Keep the controller away from power components and traces if possible. Keep sensitive traces (all sense
inputs) away from high dv/dt traces such as FET drain, FET gate drive, and auxiliary windings.
• Isolate control GND from power GND.
- All control components must be grounded to SGND.
- A single thick trace must be connected from SGND to GND and then extended to the flyback current
sense resistor R21 with a short run.
- The connection between the boost output capacitor C4 and resistor R21 must be short.
• Decouple the capacitor directly at the VDD pin of the CS1610/11 to SGND.
• Run sense traces, especially current sense, away from power-carrying traces characterized by high dv/dt
(fast rise/fall times) traces, such as collectors and drains of transistors Q2, Q3, and Q4, or the auxiliary
windings or the SOURCE pin.
• Further details are available in application note AN346 CS150x and CS160x PCB Layout Guidelines.