Cirrus Logic AN372 - Manual (Page 16)

AN372
16 AN372REV1
Notes on Circuit Fine Tuning
• Going beyond the R
FBGAIN
limitation will not have any further effect on the design.
• R
Sense
and R
FBGAIN
are frequently adjusted simultaneously to reach the desired operating point.
• The optimized final design will have a slightly different switching frequency variation than the first design
iteration.
• When the load is increased or decreased by 10%, then R
Sense
needs to be decreased or increased by less
than 10%, respectively. Adjusting R
FBGAIN
is required when the load changes so that the buck FET turn
‘ON’ hits the resonant voltage valley.
• Figure 8 illustrates a typical frequency profile with dimming. This is only one typical profile. The breakpoints
can move depending on various tolerances and specific design choices.
At this point, full power and valley switching are close to the target frequency. Further adjustment of the
frequency is done by changing the buck inductor primary inductance, L. The core gap can be changed for small
inductance variations.
5% Light
100% Light
(Full Bright)
F
sw(fb)
>F
MIN
S
w
itc
h
in
g
F
re
q
ue
nc
y,
F
sw
Further peak current reduction
and frequency increase
still reducing average current
Increasing T2 at reduced peak current
CRM with valley switching region. Reducing peak
current forces a frequency increase.
Increasing T2 at minimum peak current
Dimming
Figure 8. Buck Switching Frequency Profile vs. Dimming