Cirrus Logic AN372 - Manual (Page 20)

AN372
20 AN372REV1
Step 19) Determine Boost Input Capacitor
To be compatible with a wide range of dimmers, the boost input capacitance should be minimized. Large input
capacitance impacts the ability of the controller to properly sustain the current required by the dimmer and may
cause oscillation. Capacitors should not be connected to the AC line side of the bridge rectifier. Added AC line-
side capacitance alters the dimmer behavior in multi-lamp configurations and shifts the dimming curve.
Excessive capacitance (C1) after the bridge generates current spikes that may introduce ringing. The ringing
will cause a TRIAC to prematurely open its switches.
3.5 Completing the Design
Step 20) Choose Power Components
The voltage rating of boost FET Q2 and diode D1 can be estimated by adding 20% to the V
BST
. 20% is a
standard margin for safety purposes and prevents damage to the components during abnormal or transient
conditions. Lower voltage ratings can be used, but sufficient testing is necessary to ensure proper operation.
V
BST
is 405V or 200V for an AC input voltage of 230VAC or 120VAC, respectively. The breakdown voltage
for both the FET Q2 and the boost diode D1 ≥ (1.2  V
BST
). The boost diode must be ultrafast with a recovery
time no greater than 50ns and rated for a DC current, as calculated using Equation 23.
Step 21) Bias Circuit
The bias circuit is built using components C2, C8, C12, R4, D4, D7, and Z1 (see Figure 1 on page 4). When
AC power is first applied, current flows through capacitor C2 charging capacitor C8, which biases boost FET
Q2 into conduction. Once the bias circuit turns ‘ON’ boost FET Q2, a current is applied to pin VDD through
diode D6.
The initial supply current I
DD
flows through FET Q2 onto capacitors C10 and C6. Zener diode Z1 limits the
charge on capacitor C8.The initial supply voltage V
DD
applied to pin VDD is defined by Equation 25:.
Resistor R4 limits the current in capacitor C2. Once the voltage applied to pin VDD has exceeded the UVLO
voltage, the CS1612/13 starts to operate, and voltage appears at the boost inductor L3 auxiliary winding.
When FET Q2 is ‘ON’, capacitor C9 charges from diode D5 to pin GND. When FET Q2 is ‘OFF’, capacitor C9
reroutes the charge into capacitor C6 from diode D5. As the voltage develops across capacitor C6 and
exceeds V
DD
, FET Q1 turns ‘ON’, and diode D6 reverse biases. After startup, FET Q1 supplies V
DD
to the
device with the larger current required during normal operation. See Equation 26:
The inequality in Equation 26 indicates that D6 is back biased after start up.
Step 22) Zero-current Detection
The CS1612/13 uses zero-current detection (ZCD) to minimize switching losses. The ZCD algorithm is
designed to turn ‘ON’ the FET when the resonant voltage across the FET is at a low point (see Figure 7). Valley
switching reduces the CV
2 power losses associated with rerouting charge from the body capacitance of the
FET. Similar approaches are taken when turning ‘ON’ the boost FET Q2 and the buck FET Q4. Pin BSTAUX
and FBAUX are designed to monitor the resonant voltage from the auxiliary winding of the boost inductor L3
and the buck inductor L4, respectively. The buck ZCD and the boost ZCD function in exactly the same manner.
As described in step 21, the auxiliary winding of the boost inductor L3 is also used to drive the charge pump
circuit to develop the supply voltage, V
DD
. It is recommended to use the boost auxiliary winding for the boost
ZCD. The buck inductor L4 auxiliary winding monitors output overvoltage and the ZCD function. The auxiliary
winding turns ratio must be designed to develop ~22V peak-to-peak under nominal conditions. The turns ratio
for L4 is calculated using Equation 27:
V
DD
V
Z1
V
Q2 th  
V
D6
– – = [Eq. 25]
V
DD
V
Z1
V
Q1 th  
–   V
Z1
V
Q2 th  
V
D6
– –    = [Eq. 26]
N
P
N
AUX
--------------
V
BST
22
-------------- = [Eq. 27]