Achronix Speedster22i Memory PHY - Manual (Page 11)

UG043, April 26, 2014 11
PHY
– Controller Interfacing through Widebus
The DDR PHY in Speedster22i HD devices provides a half-rate interface to the
programmable logic fabric. Clearly, at high DDR3 data rates, running a soft controller and
the application interface at half-rate speeds is impractical and often infeasible, as far as being
able to close timing on the design.
Typically, with design complexities and fabric limitations, the target core fmax should be no
higher than 250MHz-300MHz. This means that even with a modest data rate of 1066Mbps
(half-rate clock of 266MHz), timing closure may end up being a challenge. In practice, data
rates of 1333Mbps, 1600Mbps and beyond will require a quarter-rate implementation
interface to the user logic.
Since the DDR PHY inherently does not output signals at a quarter-rate speed, a wrapper is
needed in the fabric to act as a translator between the PHY and the soft controller. This
“Widebus wrapper” takes in the half-rate clocks and signals from the PHY and outputs them
at the quarter-rate clock to the soft controller at the expense of additional latency. As a result,
quarter-rate clocks of 166.67MHz amd 200MHz would be needed at 1333Mbps and 1600Mbps
respectively.
Figure 6 below provides a block diagram view of the Widebus wrapper interface, with the
full-rate, half-rate and quarter-rate clock domains delineated within the dotted red lines.
Speedster22i
DDRxN
PHY
IO Ring
Fabric
DDR PHY
– Widebus
Interface
W
id
e
b
u
s
W
ra
p
p
e
r
Widebus –
Controller
Interface
clk_div4 clk_div2 clk_div2 clk
Quarter-rate Half-rate Full-rate
To DDRxN
Soft Controller
Figure 6: Widebus Wrapper Interface