Achronix Speedster22i Memory PHY - Manual (Page 5)

UG043, April 26, 2014 5
As stated above, there are 12 IOs in a byte-lane. A group of byte-lanes make up an IO bank
and 3 IO banks build an IO cluster (denoted using the initials EN, EC, ES, WN, WC, WS for
location). There are a total of 13 byte-lanes (or 156 IOs) per IO cluster, with the IO banks
being organized as 2 groups of 4 byte lanes and 1 group of 5 byte lanes.
Every IO cluster is powered by a separate set of power balls and so the power profile and
chacteristics of the respective rails will depend on the activity of those specific IOs.
An IO cluster is able to provide no more than 2 clocks (a half-rate and a quarter-rate) to the
corresponding triplet of clock regions. For source-synchronous operations where the clock
needs to be transmitted from the PHY to the FPGA fabric, the amount of logic that can be
clocked using this source-synchronous implementation will be limited by this architecture
(unless additional FIFOs/sync logic is used to transfer to a global clock domain in the
memory interface PHY). This concept is illustrated in Figure 2 below. Figure 3 shows a blovk
level diagram of the IO layout across the FPGA.
B
y
te
-L
a
n
e
s
0
-3
(4
8
I
O
s
)
B
y
te
L
a
n
e
s
4
-7
(4
8
I
O
s
)
B
y
te
L
a
n
e
s
8
-1
2
(6
0
I
O
s
)
Core Fabric
W
e
s
t-
N
o
rt
h
(
W
N
)
IO
C
lu
s
te
r
Clock Region West 1
Clock Region West 2
Clock Region West 3
Figure 2: Speedster22iHD IO Bank and Clock Region Organization for West North Cluster