Achronix Speedster22i sBus - Manual (Page 25)

UG047, October 24, 2013 25
sbus_cs <= ST_SBUS_WR_DATA;
end
ST_SBUS_WR : begin
if (i_sbus_ack)
sbus_cs <= ST_SBUS_IDLE;
else
sbus_cs <= ST_SBUS_WR;
end
ST_SBUS_RD_DATA :begin
if (&rdwr_data_cnt)
sbus_cs <= ST_SBUS_IDLE;
else
sbus_cs <= ST_SBUS_RD_DATA;
end
default : begin
sbus_cs <= ST_SBUS_IDLE;
end
endcase
end
end
////////////////////////////////////////////////////////////////
// Address shift counter
////////////////////////////////////////////////////////////////
always @(posedge i_clk or negedge i_rst_n)
begin
if (!i_rst_n)
address_cnt <= 'h0;
else
begin
if (sbus_cs[1])
address_cnt <= address_cnt + 1'b1;
else
address_cnt <= 'h0;
end
end
////////////////////////////////////////////////////////////////
// Parallel to serial address conversion
////////////////////////////////////////////////////////////////
always @(posedge i_clk or negedge i_rst_n)
begin
if (!i_rst_n)
addr_data_shift_in <= 'h0;
else
if (start_sbus_transfer)
addr_data_shift_in <= {write_data,addr_req};
else if (sbus_cs[1] || sbus_cs[2])
addr_data_shift_in <=
{2'b00,addr_data_shift_in[PBUS_DATA_WIDTH + 17:2]};
end
assign o_sbus_d = addr_data_shift_in[1:0];
assign sbus_req = sbus_cs[1] || sbus_cs[2];
assign o_sbus_req = sbus_req || sbus_req_dly;
always @(posedge i_clk or negedge i_rst_n)
begin
if (!i_rst_n)
o_reg_rdwr_valid <= 1'b0;
else