8 generating interrupts, Generating interrupts - 12, General interrupt enable register, bit map - 12 – Kontron CP381 User Manual

Page 54: General interrupt pending register, bit map - 12, Input irq enable register, bit map - 12, Configuration cp381

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Configuration

CP381

Page 4 - 12

© 2002 PEP Modular Computers GmbH

ID 24107, Rev. 01

4.3.8

Generating Interrupts

Any detected event or, more clearly, any event flag set in the Input Status Register can trigger
an interrupt. Thus, any input can be enabled individually for interrupt generation.

Regardless of the cause of the interrupt, a board interrupt is always handled on the hardware
level in the same way, as follows; after having set the input control registers where compare
data and events are defined, interrupts can be enabled individually within the Input IRQ Enable
Register. The final step is to enable the board interrupt in the General Interrupt Enable Register.
Within the interrupt service routine interrupts should be handled as follows.

1. Check if the board is the cause of the interrupt (General Interrupt Pending is set)
2. If yes, check the reason for the interrupt by reading the input status register
3. Reset the corresponding Input Event Flag by writing a 1 to a set status bit.
4. Reset the boards’ IRQ by resetting the General Interrupt Pending Bit by writing a 1 to that

status bit

5. Return from Interrupt

Note...

The board will continue issuing an interrupt until all interrupt sources are com-
pletely dealt with and no interrupt condition remains.

A set bit means that the boards’ interrupt is enabled.

Table 4-14: General Interrupt Enable Register, Bit Map

Bits

Type

Default

Function

31

r/w

0

Board Interrupt Enable

30 - 0

r/w

0

Reserved

Table 4-15: General Interrupt Pending Register, Bit Map

Bits

Type

Default

Function

31

r/w

0

Board Interrupt Pending

30 - 0

r/w

0

Reserved

Note...

A set bit means that the boards’ interrupt is pending. A board interrupt must be
cleared by writing a "1" to the corresponding input event flag.

Table 4-16: Input IRQ Enable Register, Bit Map

Bits

Type

Default

Function

31

r/w

0

Not used

30

r/w

0

Input compare interrupt enable

29 - 0

r/w

0

Input event interrupt enable

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