Kontron CP6-BP4-PB-RIO - Manual (Page 6)

PD18: CP6-BP4-PB-RIO CPCI Backplane
Page 6 © 2003 PEP Modular Computers GmbH RID 24229 PD18, Rev. 01
4. Signalling Environment
4.1 V(I/O) Setting
There is one block of three high-current terminals (designated as V(I/O)) for connecting V(I/O)
to either the +5V or +3.3V power supply. V(I/O) must be connected either to the +5V or the
+3.3V input power. It is the responsibility of the system integrator to ensure that the required
signalling voltage is implemented and that the backplane P1 connector coding corresponds to
the implemented signalling voltage.
4.2 P1 Connector Coding for V(I/O)
The CompactPCI Specification foresees coding of the P1 connector to correspond to the sig-
nalling environment of the PCI bus. For this reason, only boards with universal or the corre-
sponding coding can be physically inserted into the backplane. PEP’s factory default setting
for V(I/O) is +5V and male, 1567 code, brilliant blue coding keys are used.
5. Interfaces
5.1 Power
Bolt type terminals are provided for inputting DC power to this backplane. These terminals are
primarily designed for extending the DC power busses, but they can also be used with non-
pluggable power supplies for providing primary DC power input. Refer to Figure 2 for terminal
locations.
Warning!
Using both 3.3V and 5V boards within the same backplane segment
may result in damage to your equipment. Please note that the pres-
ence of only one 5V board determines a 5V signalling environment.
The default setting is 5V.
Warning!
Using boards with an inadequate signalling voltage may result in dam-
age to your equipment. Therefore, when changing the signalling envi-
ronment from 5V to 3.3V or vice versa, it is mandatory that proper
coding keys are used (refer to chapter 3 of the CPCI Backplane Man-
ual, ID 24229, for details).