CANOGA PERKINS 2240 Fiber Optic Modem User Manual
Page 68
Chapter 4 Data Interfaces
2240 Fiber Optic Modem User Manual
Programmable Buffered Interface/Model P53
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an inverter
•
a switchable delay line
The FIFO can be utilized to buffer either the received or the transmitted data (not both). The
Delay Line, in conjunction with a four-position DIP switch, provides an option for fine tuning the
relationship between clock and data timing. Table 4-17 defines the delay lines versus switch
settings for the Model P53 Interface.
A wire wrap header (J3) provides the means to interconnect these resources together with the
standard modem transmit and receive circuits to perform the intended function. Figure 4-5
illustrates how the resources are tied into the J3 header. Specific applications are satisfied by
wire wrap connections between appropriate pins.
Four pre-wrapped headers are provided with the interface. These implement the most common
applications. See the following figures: Figure 4-7, Figure 4-9, Figure 4-11, Figure 4-13.
Numerous other configurations are possible by different wired versions of the header, P3. The
four versions included are identified by part number labels affixed to the underside of the header.
The version included in the socket as shipped is P/N 610030-001 (see Figure 4-13).
The P53 can be used to interface with encryption devices on the BLACK side where modems act
as the network and supply clocking in a synchronous configuration, or to the RED (clear) side of
a data encryption (KG) equipment. In the RED side application, the interface acts as the "tail-
circuit adapter" device. This configuration allows the modem to accept two synchronous clocks
(typically, DCE devices only accept one): one for transmit (external clock) and one for receive
(FIFO input clock).
Another common application is with systems that communicate over geosynchronous satellites.
In this application, the FIFO is used to make up for clock drift (Doppler shift) caused by the
satellite's elliptical orbit around the earth.