CyClone Microsystems FEP Blade Intelligent I/O Controller COMPACTPCI-824 - Manual (Page 3)

CONTENTS
CPCI-824 User;s Manual
ii
Revision 1.0., January 2006
LIST OF FIGURES
Figure 1-1.
CPCI-824 Block Diagram ....................................................................................................1-1
Figure 1-2. CPCI-824 Physical Configuration ........................................................................................1-4
Figure 2-1. CPCI-824 Memory Map.......................................................................................................2-2
Figure 2-2. LED Register Bitmpa, E800 0001H .....................................................................................2-7
Figure 2-3 Geographic Addressing Register, B800 0001h ...................................................................2-8
Figure 2-4 Power Supply Status Register, E000 0000H.......................................................................2-9
LIST OF TABLES
Table 1-1. CPCI-824 Power Requirements .........................................................................................1-3
Table 1-2. Environmental Specifications ..............................................................................................1-3
Table 2-1. SDRAM Configurations .......................................................................................................2-3
Table 2-2. External Interrupts ...............................................................................................................2-4
Table 2-3. Console Serial Port Connector ............................................................................................2-5
Table 2-4 Gigabit Port Connector ........................................................................................................2-5
Table 2-5 10/100 Fast Port Connector ................................................................................................2-6
Table 2-6 Breeze Start-up LEDs..........................................................................................................2-8
Table 2-7 I
2
C Device Addresses .......................................................................................................2-10
Table 2-8 JTAG Emulator Pin Assignment ........................................................................................2-11
Table A-1. PMC Clock & Arbitration Assignment ................................................................................. A-2
Table A-2. PMC Interrupt Assignment ................................................................................................. A-2
Table A-3. P21 PMC Module Connector Pinout................................................................................... A-3
Table A-4. P22 PMC Module Connector Pinout................................................................................... A-4
Table A-5. P23 PMC Module Connector Pinout................................................................................... A-5
Table B-1. CPCI-821 J2 Definition ....................................................................................................... B-1