Cypress CY7C1383DV25 - Manual (Page 6)

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E Page 6 of 28
Pin Definitions
Name IO Description
A
0
, A
1
, A Input-
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
[2] are sampled active.
A
[1:0]
feed the 2-bit counter.
BW
A
, BW
B
BW
C
, BW
D
Input-
Synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW Input-
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
[A:D]
and BWE).
CLK Input-
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
CE
1
Input-
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
2
and CE
3
[2] to select or deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only when a new external address is loaded.
CE
2
Input-
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
[2] to select or deselect the device. CE
2
is sampled only when a new
external address is loaded.
CE
3
[2]
Input-
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
2
to select or deselect the device. CE
3
is sampled only when a new external
address is loaded.
OE Input-
Asynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV Input-
Synchronous
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP Input-
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
ADSC Input-
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
BWE Input-
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
ZZ Input-
Asynchronous
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull down.
DQ
s
IO-
Synchronous
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQ
s
and DQP
X
are placed in a tri-state condition.The outputs are
automatically tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected, regardless of
the state of OE.
DQP
X
IO-
Synchronous
Bidirectional data parity IO lines. Functionally, these signals are identical to DQ
s
. During
write sequences, DQP
X
is controlled by BW
X
correspondingly.
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