Ac switching characteristics, Switching waveforms – Cypress Perform nvSRAM User Manual
Page 9
PRELIMINARY
CY14B102L, CY14B102N
Document #: 001-45754 Rev. *B
Page 9 of 24
AC Switching Characteristics
Parameters
Description
20 ns
25 ns
45 ns
Unit
Cypress
Parameters
Alt
Parameters
Min
Max
Min
Max
Min
Max
SRAM Read Cycle
t
ACE
t
ACS
Chip Enable Access Time
20
25
45
ns
t
RC
t
RC
Read Cycle Time
20
25
45
ns
t
AA
t
AA
Address Access Time
20
25
45
ns
t
DOE
t
OE
Output Enable to Data Valid
10
12
20
ns
t
OHA
t
OH
Output Hold After Address Change
3
3
3
ns
t
LZCE
t
LZ
Chip Enable to Output Active
3
3
3
ns
t
HZCE
t
HZ
Chip Disable to Output Inactive
8
10
15
ns
t
LZOE
t
OLZ
Output Enable to Output Active
0
0
0
ns
t
HZOE
t
OHZ
Output Disable to Output Inactive
8
10
15
ns
t
PU
t
PA
Chip Enable to Power Active
0
0
0
ns
t
PD
t
PS
Chip Disable to Power Standby
20
25
45
ns
t
DBE
-
Byte Enable to Data Valid
10
12
20
ns
t
LZBE
-
Byte Enable to Output Active
0
0
0
ns
t
HZBE
-
Byte Disable to Output Inactive
8
10
15
ns
SRAM Write Cycle
t
WC
t
WC
Write Cycle Time
20
25
45
ns
t
PWE
t
WP
Write Pulse Width
15
20
30
ns
t
SCE
t
CW
Chip Enable To End of Write
15
20
30
ns
t
SD
t
DW
Data Setup to End of Write
8
10
15
ns
t
HD
t
DH
Data Hold After End of Write
0
0
0
ns
t
AW
t
AW
Address Setup to End of Write
15
20
30
ns
t
SA
t
AS
Address Setup to Start of Write
0
0
0
ns
t
HA
t
WR
Address Hold After End of Write
0
0
0
ns
t
HZWE
t
WZ
Write Enable to Output Disable
8
10
15
ns
t
LZWE
t
OW
Output Active after End of Write
3
3
3
ns
t
BW
-
Byte Enable to End of Write
15
20
30
ns
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled
$GGUHVV
'DWD2XWSXW
$GGUHVV9DOLG
3UHYLRXV'DWD9DOLG
2XWSXW'DWD9DOLG
W
5&
W
$$
W
2+$
Notes
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE, OE and BHE / BLE LOW.
17. Measured ±200 mV from steady state output voltage.
18. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
19. HSB must remain HIGH during READ and WRITE cycles.