Maxim Integrated 71M6521BE Energy Meter IC Family Software - Manual (Page 128)

71M652X Software User’s Guide
Revision 1.7 TERIDIAN Proprietary 128 of 138
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
IP0.6 WDTS Watchdog timer status flag. Set by hardware when the watchdog timer was
started. Can be read by software.
Table 6-38: The IP0 Bit Functions
Note: The remaining bits in the IP0 register are not used for watchdog control
Watchdog Timer Reload Register (WDTREL):
MSB LSB
7 6 5 4 3 2 1 0
Table 6-39: The WDTREL Register
Bit Symbol Function
WDTREL.7 7 Prescaler select bit. When set, the watchdog is clocked through an additional
divide-by-16 prescaler
WDTREL.6
to
WDTREL.0
6-0 Seven bit reload value for the high-byte of the watchdog timer. This value is
loaded to the WDT when a refresh is triggered by a consecutive setting of bits
WDT and SWDT.
Table 6-40: The WDTREL Bit Functions
The WDTREL register can be loaded and read at any time.
6.3.5 The Interrupt Service Routine Unit
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a
special function register (TCON, IRCON, SCON). Each interrupt requested by the corresponding flag can be
individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and IEN2.
6.3.5.1 Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 6-58. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a
return from instruction, "RETI". When an RETI is performed, the processor will return to the instruction that would have
been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are
polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt
request flag is set. On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to
the appropriate vector address, if the following conditions are met:
● No interrupt of equal or higher priority is already in progress.
● An instruction is currently being executed and is not completed.
● The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Interrupt response will require a varying amount of time depending on the state of the MPU when the interrupt occurs. If
the MPU is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In other
cases, the response time depends on the current instruction. The fastest possible response to an interrupt is 7 machine
cycles. This includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL.
6.3.5.2 Special Function Registers for Interrupts
Interrupt Enable 0 Register (IE0)
MSB LSB