Maxim Integrated MAXQ622 - Manual (Page 174)

MAXQ612/MAXQ622 User’s Guide
12-4 Maxim Integrated
This register is used to supply the offset location and control read/write access to the internal USB registers .
Bit 7: USB Register Read/Write Select (USBRW). When this bit is set to 1, the CPU initiates a read operation to the
register at offset UADDR[4:0] . When cleared to 0, the CPU waits for data to be loaded to UDATA before initiating a
write operation to the register at offset UADDR[4:0] .
Bit 6: USB Busy (UBUSY). This active-high busy flag sets to logic 1 to indicate the start of a USB register read/write
operation . It is held high until the end of the operation .
Bit 5: Reserved. Reads returns zero.
Bits 4 to 0: USB Register Address (UADDR[4:0]). These register bits are used to supply the offset location for
accessing internal USB register . Valid offset locations are listed in the following table:
12.3 USB Peripheral Register Descriptions
The following peripheral registers are used to control the USB functions .
12.3.1 USB Register Address Register
Note: Writes to this register are ignored when UBUSY = 1.
Register Name UADDR
Register Description USB Register Address Register
Register Address M4[04h]
Bit # 7 6 5 4 3 2 1 0
Name USBRW UBUSY — UADDR4 UADDR3 UADDR2 UADDR1 UADDR0
Reset 0 0 0 0 0 0 0 0
Access rw r rw rw rw rw rw rw
OFFSET REGISTER DESCRIPTION
00h — Idle—No operation
01h FNADDR Function Address Register
02h USBCN USB Control Register
03h USBCFG USB Configuration Register
04h USBIEN USB Interrupt Enable Register
05h USBINT USB Interrupt Register
06h EPIEN Endpoint Interrupt Enable Register
07h EPINT Endpoint Interrupt Register
08h EPSTL Endpoint Stall Register
09h EPNAK Endpoint NAK Register
0Ah EPCTG Endpoint Clear Data Toggle Register
0Bh EP0BC Endpoint 0 Byte Count Register
0Ch EP1BC Endpoint 1 Byte Count Register
0Dh EP2BC Endpoint 2 Byte Count Register
0Eh EP3BC Endpoint 3 Byte Count Register
0Fh Reserved No operation
10h EP0BUF Endpoint 0 Buffer Register
11h EP1BUF Endpoint 1 Buffer Register
12h EP2BUF Endpoint 2 Buffer Register
13h EP3BUF Endpoint 3 Buffer Register
14h SUDBUF Setup Data Buffer Register
1F–15h Reserved No operation