Maxim Integrated MAXQ622 - Manual (Page 30)

MAXQ612/MAXQ622 User’s Guide
2-26 Maxim Integrated
2.8.1 Using the Wake-Up Timer to Exit Stop Mode
To use the wake-up timer to exit stop mode after a predefined period of time, the following conditions must be met
before entering stop mode:
• The WUT register must be written to define the countdown interval value.
• The WTE bit must be written to 1 to start the wake-up timer .
• The IGE (IC.0) bit must be set to 1 to enable global interrupts. The wake-up timer cannot wake the MAXQ612/
MAXQ622 up from stop mode if its interrupt does not fire .
2.9 Interrupts
The MAXQ612/MAXQ622 provide a hardware interrupt handler with interrupt vector (IV) table base address register
and the interrupt control (IC) register . The IV register is fixed at 0020h and acts as the vector table base location .
Interrupts can be generated from system level sources (e .g ., watchdog timer) or by sources associated the peripheral
modules . The interrupt vectors are preset at eight fixed memory address offsets from IV with hardware priority control
that can be programmed through the interrupt priority register zero (IPR0 and IPR1) .
2.9.1 Servicing Interrupts
For the MAXQ612/MAXQ622 to service an interrupt, interrupt handling must be enabled globally and locally . The IGE
bit located in the IC register acts as a global interrupt mask that affects all interrupts, with the exception of the power-
fail warning interrupt . This bit defaults to 0, and it must be set to 1 before any interrupt handling takes place .
The local interrupt-enable bit for a particular source is in one of the peripheral registers associated with that peripheral
module or in a system register for any system interrupt source . When an interrupt condition occurs, its individual flag
is set, even if the interrupt source is disabled at the local or global level . Interrupt flags must be cleared within the user
interrupt routine to avoid repeated interrupts from the same source .
The handler uses three levels of interrupt priorities that allow the user software to select a suitable priority for an inter-
rupt vector source . The interrupt handler (hardware) modifies the interrupt priority status bits (IPSn) when it is servicing
an interrupt . These bits are set to 11b by the interrupt handler when executing a RETI instruction .
2.9.2 Interrupt System Operation
The interrupt handler responds to any interrupt event when it is enabled . An interrupt event occurs when an interrupt
flag is set . All interrupt requests are sampled at the rising edge of the clock, and can be served by the processor one
clock cycle later, assuming the request does not hit the interrupt exception window . The one cycle stall between detec-
tion and acknowledgement/servicing is due to the fact that the current instruction could also be accessing the stack,
or that the current instruction could be a prefix register (PFX[n]) write . For this reason, the CPU must allow the current
instruction to complete before pushing the stack and vectoring to the proper interrupt vector table address . If an inter-
rupt exception window is generated by the currently executing instruction, the following instruction must be executed,
thus the interrupt service routine is delayed an additional cycle .
Interrupt operation in the MAXQ612/MAXQ622 CPU is essentially a state-machine-generated long CALL instruc-
tion . When the interrupt handler services an interrupt, it temporarily takes control of the CPU to perform the following
sequence of actions:
1) The next instruction fetch from program memory is cancelled .
2) The return address is pushed on to the stack .
3) The IPS bits are set to the current interrupt level to prevent recursive interrupt calls from interrupts of lower priority .
4) The instruction pointer is set to the location of the interrupt service routine as defined by the interrupt source .
5) The CPU begins executing the interrupt service routine .
Once the interrupt service routine completes, it should use the RETI instruction to return to the main program . Execution
of RETI involves the following sequence of actions:
1) The return address is popped off the stack .