Maxim Integrated MAXQ Family Users Guide: MAXQ2010 Supplement - Manual (Page 67)

MAXQ Family User’s Guide:
MAXQ2010 Supplement
14-5
Bit 15: RTC Write Enable (WE). This register bit serves as a protection mechanism against undesirable writes to the
RTCE bit and RTRM register. This bit must be set to a 1 to give write access to the RTRM register and the RTCE bit;
otherwise (when WE bit = 0) these protected bits are read-only.
Bit 14: Reserved. Read returns 1 after reset, or last written value (when BUSY = 0).
Bit 13: Alternate Clock Select (ACS). This bit enables the use of the system clock to drive the RTC in place of the
32kHz clock. When the alternate clock is selected (ACS = 1), the RTC input clock is driven by system clock/128. This
bit is provided for those applications where a 32kHz clock may not be present, or when the RTC module is intended
to be used as a timer based on the system clock. This bit can only be changed when RTCE = 0. When ACS = 1, the
RTC is effectively halted any time that the system clock is disabled (e.g., stop mode).
Bits 12:10: Reserved. Read returns zero.
Bit 9: RTC Frequency Test (FT). This register bit selects the frequency output on the SQW pin if the square-wave out-
put is enabled (SQE = 1). Setting FT = 1 selects the RTC input clock/8 output (512Hz for 32.768kHz applied to 32KIN),
while FT = 0 selects the RTC input clock/4096 (1Hz for 32.768kHz applied to 32KIN). This bit has no function when the
square-wave output is disabled (SQE = 0).
Bit 8: RTC Square-Wave Output Enable (SQE). Setting this bit to 1 enables the frequency specified by FT to be
outputted to the SQW pin. When cleared to 0, the SQW pin is not driven by the RTC.
Bit 7: Alarm Subsecond Flag (ALSF). This bit is set when the subsecond timer has been reloaded by the RSSA reg-
ister. Setting the ALSF causes an interrupt request to the CPU if the ASE is set and interrupt is allowed at the system
level. This flag must be cleared by software once set. This alarm is qualified as wake-up to the stop and the switchback
function if its interrupt has not been masked.
Bit 6: Alarm Time-of-Day Flag (ALDF). This bit is set when the contents of RTSH and RTSL counter registers match
the 20-bit value in the RASH and RASL alarm registers. Setting the ALDF causes an interrupt request to the CPU if the
ADE is set and interrupt is allowed at the system level. This flag must be cleared by software once set. This alarm is
qualified as wake-up to the stop and the switchback function if its interrupt has not been masked.
Bit 5: RTC Ready Enable (RDYE). Setting this bit to 1 allows a system interrupt to be generated when RDY becomes
active (if interrupts are enabled globally and modularly). Clearing this bit to 0 disables the RDY interrupt.
Bit 4: RTC Ready (RDY). This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to
0 by software at any time. It is also cleared to 0 by hardware just prior to an update of the RTC count register. This bit
can generate an interrupt if the RDYE bit is set to 1
Bit 3: RTC Busy (BUSY). This bit is set to 1 by hardware when any of the following conditions occur:
1) System reset.
2) Software writes to RTC count registers or trim register.
3) Software changes RTCE, ASE, or ADE.
For conditions 2 and 3, the write or change should not be considered complete until hardware clears the BUSY bit.
This is an indication that a 32kHz synchronized version of the register bit(s) is in place.
Bit 2: Alarm Subsecond Enable (ASE). The ASE bit is the RTC’s subsecond timer enable and must be set to logic 1
for the subsecond alarm to generate a system interrupt request. When the ASE is cleared to logic 0, the subsecond
alarm is disabled and no interrupt is generated, even if the alarm is set.
Bit 1: Alarm Time-of-Day Enable (ADE). The ADE bit is the RTC’s time-of-day alarm enable and must be set to logic
1 for the alarm to generate a system interrupt request. When the ADE is cleared to logic 0, the time-of-day alarm is
disabled and no interrupt is generated, even if the alarm is set.
Bit 0: RTC Enable (RTCE). Setting this bit to logic 1 activates the clocking by allowing the divided clock to the ripple
counters. Clearing this bit to logic 0 disables the clock.