Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 103)

DS4830 User’s Guide
103
12.4 – SPI Master
The DS4830 has the following SPI interface signals.
Functional name External pin name
MSPIDI: Input to serial shift register (MISO) MDI
MSPIDO: Output from serial shift register (MOSI) MDIO
MSPICK: Serial shift clock sourced to slave device(s) (SPICK) MCL
MSPICS: (Optional) Mode fault detection input if enabled (MODFE=1) (SSEL) MCS
12.4.1 – SPI Transfer Baud Rates
When operating in the master mode, the SPI serial clock is sourced to the external slave device(s). The serial clock baud
rate is determined by the clock divide ratio specified in the SPI Clock Divider Ratio (SPICK) register. The SPI module
supports 256 different clock divide ratio selections for serial clock generation. The SPI Baud rate is determined by the
following formula:
12.4.2 – SPI Master Operation
The SPI module is placed in master mode by setting the Master Mode Enable (MSTM) bit in the SPI Control register to 1.
Only an SPI master device can initiate a data transfer. The master is responsible for manually selecting/deselecting
slave(s) via the MSPICS signal or any GPIO pin. Writing a data character to the SPI shift register (SPIB) while in master
mode starts a data transfer. The SPI master immediately shifts out the data serially on the MSPIDO pin, most significant
bit first, while providing the serial clock on MSPICK output. New data is simultaneously received on the MSPIDI pin into
the least significant bit of the shift register. The data transfer format (clock polarity and phase), character length, and baud
rate are all configurable as described earlier in the section. During the transfer, the SPI Transfer Busy (SPICN.7:STBY)
flag will be set to indicate that a transfer is in process. At the end of the transfer, the data contained in the shift register is
moved into the receive data buffer, the STBY bit is cleared by hardware, and the SPI Transfer Complete flag (SPICN.6:
SPIC) is set. Setting of the SPIC bit will generate an interrupt request if SPI interrupt sources are enabled (ESPII=1).
The SPI master can be configured to transfer either 8 or 16 bits in an operation to accommodate network with different
word length requirements. The data transfer rate for the network is determined by the divider ratio in the master’s SPI
Clock SFR. The SPI transfer format is selected by the master device using two bits SPI Clock Polarity (CKPOL) and Clock
Phase in the SPI Configuration Register.
SPI Baud Rate =
System Clock Frequency
2 * Clock Divide Ratio
Where Clock Divider Ratio = (SPICK.7:0) + 1