Receive elasticity buffer, Receive modes, Power control – Cypress CYV15G0404DXB User Manual
Page 18: Device reset state, Output bus
CYV15G0404DXB
Document #: 38-02097 Rev. *B
Page 18 of 44
Code rule violations or running disparity errors that occur as part
of the BIST loop do not cause an error indication. RXSTx[2:0]
indicates 010b or 100b for one character period per BIST loop to
indicate loop completion. This status can be used to check test
pattern progress. These same status values are presented when
the decoder is bypassed and BIST is enabled on a receive
channel.
The specific status reported by the BIST state machine are listed
in
. These same codes are reported on the receive
status outputs.
The specific patterns checked by each receiver are described in
detail in the Cypress application note “HOTLink Built-In
Self-Test.” The sequence compared by the CYV15G0404DXB is
identical to that in the CY7B933, CY7C924DX, and
CYP(V)15G0401DXB, allowing interoperable systems to be built
when used at compatible serial signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR to
the D0.0 state to look for the start of the BIST sequence again.
When Receive BIST is enabled on a channel, do not enable the
low latency framer. The BIST sequence contains an aliased
K28.5 framing character, which causes the receiver to update its
character boundaries incorrectly.
The receive BIST state machine requires the characters to be
correctly framed for it to detect the BIST sequence. If the low
latency framer is enabled, the framer misaligns to an aliased
SYNC character within the BIST sequence. If the alternate
multi-byte framer is enabled and the receiver outputs are clocked
relative to a recovered clock, it is generally necessary to frame
the receiver before BIST is enabled. If the receive outputs are
clocked relative to REFCLKx±, the transmitter precedes every
511 character BIST sequence with a 16 character word sync
sequence.
A device reset (RESET sampled LOW) presets the BIST enable
latches to disable BIST on all channels.
Receive Elasticity Buffer
Each receive channel contains an elasticity buffer that is
designed to support multiple clocking modes. These buffers
allow data to be read using a clock that is asynchronous in both
frequency and phase from the elasticity buffer write clock, or to
be read using a clock that is frequency coherent but with uncon-
trolled phase relative to the elasticity buffer write clock.
If the chip is configured for operation with a recovered clock, the
elasticity buffer is bypassed.
Each elasticity buffer is 10 characters deep, and supports and an
11 bit wide data path. It is capable of supporting a decoded
character and three status bits for each character present in the
buffer. The write clock for these buffers is always the recovered
clock for the associated read channel.
Receive Modes
When the receive channel is clocked by REFCLKx±, the
RXCLKx± outputs present a buffered or divided (depending on
RXRATEx) and delayed form of REFCLKx±. In this mode, the
receive elasticity buffers are enabled. For REFCLKx± clocking,
the elasticity buffers must be able to insert K28.5 characters and
delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel. However, the actual timing of
these insertions and deletions is controlled in part by how the
transmitter sends its data. Insertion of a K28.5 character can only
occur when the receiver has a framing character in the elasticity
buffer. Likewise, to delete a framing character, one must also be
in the elasticity buffer. To prevent a buffer overflow or underflow
on a receive channel, a minimum density of framing characters
must be present in the received data streams.
When the receive channel output register is clocked by a
recovered clock, no characters are added or deleted and the
receiver elasticity buffer is bypassed.
Power Control
The CYV15G0404DXB supports user control of the powered up
or down state of each transmit and receive channel. The receive
channels are controlled by the RXPLLPDx latch through the
device configuration interface. When RXPLLPDx = 0, the
associated PLL and analog circuitry of the channel is disabled.
The transmit channels are controlled by the OE1x and the OE2x
latches through the device configuration interface. When a driver
is disabled through the configuration interface, it is internally
powered down to reduce device power. If both serial drivers for
a channel are in this disabled state, the associated internal logic
for that channel is powered down as well.
Device Reset State
When the CYV15G0404DXB is reset by assertion of RESET, all
state machines, counters, and configuration latches in the device
are initialized to a reset state, and the elasticity buffer pointers
are set to a nominal offset. Additionally, the JTAG controller must
also be reset to ensure valid operation (even if JTAG testing is
not performed). See the
section for JTAG state
machine initialization. See
for the initialize values of the
configuration latches.
Following a device reset, it is necessary to enable the transmit
and receive channels used for normal operation. This is done by
sequencing the appropriate values on the device configuration
interface.
Output Bus
Each receive channel presents an 11-signal output bus
consisting of
■
An 8-bit data bus
■
A 3-bit status bus.
The signals present on this output bus are modified by the
present operating mode of the CYV15G0404DXB as selected by
the DECBYPx configuration latch. This mapping is shown in
Note
11. When the receive paths are configured for REFCLKx± operation, each pass must be preceded by a 16-character Word Sync Sequence to allow management
of clock frequency variations.