Altera Cyclone V GT FPGA Development Board - Manual (Page 40)

2–32 Chapter 2: Board Components
Components and Interfaces
Cyclone V GT FPGA Development Board September 2014 Altera Corporation
Reference Manual
18 HSMB_RX_P3 G2 1.5-V PCML Transceiver RX bit 3
19 HSMB_TX_N3 F3 1.5-V PCML Transceiver TX bit 3n
20 HSMB_RX_N3 G1 1.5-V PCML Transceiver RX bit 3n
21 HSMB_TX_P2 H4 1.5-V PCML Transceiver TX bit 2
22 HSMB_RX_P2 J2 1.5-V PCML Transceiver RX bit 2
23 HSMB_TX_N2 H3 1.5-V PCML Transceiver TX bit 2n
24 HSMB_RX_N2 J1 1.5-V PCML Transceiver RX bit 2n
25 HSMB_TX_P1 K4 1.5-V PCML Transceiver TX bit 1
26 HSMB_RX_P1 L2 1.5-V PCML Transceiver RX bit 1
27 HSMB_TX_N1 K3 1.5-V PCML Transceiver TX bit 1n
28 HSMB_RX_N1 L1 1.5-V PCML Transceiver RX bit 1n
29 HSMB_TX_P0 M4 1.5-V PCML Transceiver TX bit 0
30 HSMB_RX_P0 N2 1.5-V PCML Transceiver RX bit 0
31 HSMB_TX_N0 M3 1.5-V PCML Transceiver TX bit 0n
32 HSMB_RX_N0 N1 1.5-V PCML Transceiver RX bit 0n
33 HSMB_SDA L20 2.5-V CMOS Management serial data
34 HSMB_SCL E27 2.5-V CMOS Management serial clock
35 JTAG_TCK AK5 2.5-V CMOS JTAG clock signal
36 HSMB_JTAG_TMS — 2.5-V CMOS JTAG mode select signal
37 HSMB_JTAG_TDO — 2.5-V CMOS JTAG data output
38 HSMB_JTAG_TDI — 2.5-V CMOS JTAG data input
39 HSMB_CLK_OUT0 D25 2.5-V CMOS Dedicated CMOS clock out
40 HSMB_CLK_IN0 A22 2.5-V CMOS Dedicated CMOS clock in
41 HSMB_WEn B24 2.5-V CMOS Write enable
42 HSMB_RASn A23 2.5-V CMOS Row address select
43 HSMB_ADDR_CMD0 L18 2.5-V CMOS Memory address or command
44 HSMB_CASn C21 2.5-V CMOS Column address select
47 HSMB_DQ0 E22 2.5-V CMOS Memory data bus
49 HSMB_DQ1 G20 2.5-V CMOS Memory data bus
53 HSMB_DQ2 F20 2.5-V CMOS Memory data bus
55 HSMB_DQ3 D24 2.5-V CMOS Memory data bus
59 HSMB_DQ4 C26 2.5-V CMOS Memory data bus
61 HSMB_DQ5 G21 2.5-V CMOS Memory data bus
65 HSMB_DQ6 F21 2.5-V CMOS Memory data bus
67 HSMB_DQ7 D27 2.5-V CMOS Memory data bus
71 HSMB_DQ8 F23 2.5-V CMOS Memory data bus
73 HSMB_DQ9 C29 2.5-V CMOS Memory data bus
77 HSMB_DQ10 E24 2.5-V CMOS Memory data bus
79 HSMB_DQ11 H21 2.5-V CMOS Memory data bus
Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)
Board
Reference
Schematic Signal Name
Cyclone V GT
Pin Number
I/O Standard Description