Altera Transceiver Signal Integrity Development Kit, Stratix IV GT Edition - Manual (Page 35)

Chapter 2: Board Components 2–25
Power
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
Table 2–28 summarizes the transceiver channels available on the Stratix IV GT
transceiver signal integrity development board.
All receive channels include a 0402 type 0.1-µF DC blocking capacitor in series with
the P and N signals to remove the DC component of the transmitted signal. The
receivers internally regenerate the required DC offset. Blocking capacitors are not
provided for transmit channels.
Power
The board’s power is provided through a laptop style DC power input. The input
voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to
the various power rails used by the components on the board. The slide switch (SW1)
is the board power switch.
Table 2–28. Transceiver Channel Pin-Out
Board
Reference
Description Schematic Signal Name
I/O
Standard
Stratix IV GT
Device Pin
Number
Other
Connections
J70 TX0 from Left GXB0 Block GXB0_TX0[p/n] — AT36, AT37 J70.F6, J70.E6
J70 TX1 from Left GXB0 Block GXB0_TX1[p/n] — AP36, AP37 J70.E5, J70.D5
J70 TX2 from Left GXB0 Block GXB0_TX2[p/n] — AH36, AH37 J70.L4, J70.K4
J70 TX3 from Left GXB0 Block GXB0_TX3[p/n] — AF36, AF37 J70.K3, J70.J3
J70 TX4 from Left GXB0 Block GXB0_CMU_TX4[p/n] — AM36, AM37 J70.F4, J70.E4
J70 TX5 from Left GXB0 Block GXB0_CMU_TX5[p/n] — AK36, AK37 J70.E3, J70.D3
J71 RX0 from Left GXB0 Block GXB0_RX0[p/n] — AU38, AU39 J71.F6, J71.E6
J71 RX1 from Left GXB0 Block GXB0_RX1[p/n] — AR38, AR39 J71.E5, J71.D5
J71 RX2 from Left GXB0 Block GXB0_RX2[p/n] — AJ38, AJ39 J71.L4, J71.K4
J71 RX3 from Left GXB0 Block GXB0_RX3[p/n] — AG38, AG39 J71.K3, J71.J3
J71 RX4 from Left GXB0 Block GXB0_CMU_RX4[p/n] — AN38, AN39 J71.F4, J71.E4
J71 RX5 from Left GXB0 Block GXB0_CMU_RX5[p/n] — AL38, AL39 J71.E3, J71.D3
J39, J41 TX0 from Left GXB1 Block GXB1_TX0[p/n] — AD36, AD37 —
J38, J40 RX0 from Left GXB1 Block GXB1_RX0[p/n] — AE38, AE39 —
J43, J45 TX1 from Left GXB1 Block GXB1_TX1[p/n] — AB36, AB37 —
J42, J44 RX1 from Left GXB1 Block GXB1_RX1[p/n] — AC38, AC39 —
J55, J57 TX2 from Left GXB1 Block GXB1_TX2[p/n] — T36, T37 —
J54, J56 RX2 from Left GXB1 Block GXB1_RX2[p/n] — U38, U39 —
J59, J61 TX3 from Left GXB1 Block GXB1_TX3[p/n] — P36, P37 —
J58, J60 RX3 from Left GXB1 Block GXB1_RX3[p/n] — R38, R39 —
J34, J36 TX0 from Left GXB2 Block GXB2_TX0[p/n] — M36, M37 —
J30, J32 RX0 from Left GXB2 Block GXB2_RX0[p/n] — N38, N39 —
J31, J33
15 inches long transmitter TX1
channel from Left GXB2 Block
GXB2_TX1[p/n] — K36, K37 —
J35, J37
5 inches long receiver RX1
channel from Left GXB2 Block
GXB2_RX1[p/n] — L38, L39 —