Zilog EZ80F91 - Manual (Page 53)

eZ80F91 Development Kit
User Manual
UM014220-0508 eZ80F91 Module
48
eZ80F91 Module Memory
Static RAM
The eZ80F91 Module features 512 KB of fast SRAM. Access speed is
typically 12 ns, allowing zero-wait-state operation at 50 MHz. With the
CPU at 50 MHz, SRAM can be accessed with zero wait states in eZ80
mode. CS1_CTL (CS1) can be set to
08h (no wait states).
Flash Memory
The eZ80F91 Module features 256 KB of on-chip Flash memory, which
can be programmed a single byte at a time, or in bursts of up to 128 bytes.
Write operations can be performed using either memory or I/O instruc-
tions. Erasing bytes in Flash memory returns them to a value of
FFh . Both
the MASS ERASE and PAGE ERASE operations are self-timed by the
Flash controller, leaving the CPU free to execute other operations in par-
allel. Upon power-up, the on-chip Flash memory is located in the address
range
000000h–03FFFFh . Four wait states are programmed in Flash
control register F8h .
On-chip Flash memory is prioritized over all external Chip Selects, can be
enabled or disabled (power-on enabled), and can be programmed within
any 256 KB address space in the 16 MB address range.
The eZ80F91 Module features the following memory configurations:
•
On-chip SRAM: 8 KB
•
Off-chip SRAM: 512 KB
•
On-chip Flash: 256 KB
Reset Generator
An onboard supervisory chip is connected to the eZ80F91 Reset input
pin. It performs reliable Power-On Reset functions, generating a reset
pulse with a duration of 200 ms if the power supply drops below 2.93 V.
This reset pulse ensures that the board always starts in a defined