Artesyn ATCA-9405 Installation and Use (May 2014) User Manual
Atca-9405
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Table of contents
Document Outline
- ATCA-9405
- Regulatory Agency Warnings & Notices
- Contents
- About this Manual
- Introduction
- Setup
- Packet Processor
- 3.1 Overview
- 3.2 CN6880 Processor
- 3.3 Cache
- 3.4 System Memory
- 3.5 Octeon U-Boot
- 3.6 SerDes Configuration
- 3.7 PCI Express Interface
- 3.8 Ethernet Interface
- 3.9 Interlaken Interface
- 3.10 USB Interface
- 3.11 UART Interface
- 3.12 I2C Interface
- 3.13 JTAG Interface
- 3.14 Interrupts
- 3.15 Power Supply
- 3.16 Cooling
- Service Processor
- 4.1 Overview
- 4.2 P2020 Processor
- 4.3 Cache
- 4.4 Main Memory
- 4.5 SP U-Boot
- 4.6 Local Bus
- 4.7 SerDes Configuration
- 4.8 PCI Express Interface
- 4.9 Ethernet Interface
- 4.10 SPI Interface
- 4.11 USB Interface
- 4.12 UART Interface
- 4.13 I2C Interface
- 4.14 JTAG Interface
- 4.15 Interrupts
- 4.16 Cooling
- Ethernet Infrastructure
- Service Infrastructure
- Mezzanine Module
- Intelligent Peripheral Management Controller
- 8.1 Overview
- 8.2 Functional Overview
- 8.3 Firmware Architecture
- 8.4 HPM.1 Components
- 8.5 Sensors
- 8.6 POST
- 8.7 FRU Inventory
- 8.8 Reset and Power Domains
- 8.9 Power Management
- 8.10 U-Boot Boot Configuration Parameters
- 8.11 Asynchronous Event Notification
- 8.12 Serial Line Selection
- 8.13 Built-in Terminal Server
- 8.14 Fail Safe Logic and Watchdog Support
- 8.15 Payload Interface
- 8.16 Payload Boot Bank Selection
- 8.17 Settable Graceful Shutdown Timeout
- 8.18 FPGA Health Check
- 8.19 Local System Event Log (SEL)
- 8.20 IPMI Hardware Watchdog
- 8.21 Artesyn OEM Command Set
- A Related Documentation
- Safety Notes
- Sicherheitshinweise