Artesyn ATCA-9405 Installation and Use (May 2014) - Manual (Page 112)

Intelligent Peripheral Management Controller
ATCA-9405 Installation and Use (6806800M71G) 112
 Serial Line Selection
 Built-in Terminal Server
 Settable Graceful Shutdown Timeout
 IPMI Hardware Watchdog Timer
 Fail-safe
 Local System Event Log (SEL)
The IPMC at the front board actslike a carrier IPMC. It retrieves the sensor information of the
MMC and creates an SDR repository that provides direct access to all sensors within the
system. The IPMC is implemented as the managed FRU #0 and the MMC as FRU #1. All
commands which are directed to the MMC are bridged by the IPMC.
The P2020 communicates with the IPMC using the Keyboard Controller Style (KCS) interface of
the H8S. The FRU inventory, SEL events, and the SDR information is stored in external I2C
EEPROMS. This enables post-mortem analysis, when the system processor is disabled.
IPMB buffers on both the IPMB-0 busses are used to isolate a faulty IPMB bus from the
backplane.
IPMC can access the registers within the FPGA and the Power CPLD via SPI bus. This enhances
the capabilities of the IPMC. The FPGA is used to monitor the CPU status, the Payload reset
cause, and to control the boot bank selection. The Power CPLD controls the enabling and
monitoring of power good signals from all on-board power converters.
The functional block diagram of the ATCA-9405 IPMC/MMC system is shown in Figure 8-1 on
page 113 .