Artesyn MVME3100 Single Board Computer Installation and Use (June 2014) User Manual
Mvme3100 single board computer
Advertising
Table of contents
Document Outline
- MVME3100 Single Board Computer
- Contents
- About this Manual
- Hardware Preparation and Installation
- Startup and Operation
- MOTLoad Firmware
- 3.1 Overview
- 3.2 Implementation and Memory Requirements
- 3.3 MOTLoad Commands
- 3.4 Using the Command Line Interface
- 3.5 Firmware Settings
- 3.6 Remote Start
- 3.7 Alternate Boot Images and Safe Start
- 3.8 Firmware Startup Sequence Following Reset
- 3.9 Firmware Scan for Boot Image
- 3.10 Boot Images
- 3.11 Startup Sequence
- Functional Description
- 4.1 Overview
- 4.2 Features
- 4.3 Block Diagrams
- 4.4 Processor
- 4.5 System Memory
- 4.6 Local Bus Interface
- 4.7 I2C Serial Interface and Devices
- 4.8 Ethernet Interfaces
- 4.9 Asynchronous Serial Ports
- 4.10 PCI/PCI-X Interfaces and Devices
- 4.11 General-Purpose Timers
- 4.12 Real-time Clock Battery
- 4.13 Reset Control Logic
- 4.14 Debug Support
- Pin Assignments
- 5.1 Overview
- 5.2 Connectors
- 5.2.1 PMC Expansion Connector (J4)
- 5.2.2 Ethernet Connectors (GENET1/J41B, GENET2/J2B, ENET1/J2A)
- 5.2.3 PCI Mezzanine Card (PMC) Connectors (J11 – J14, J21 – J23)
- 5.2.4 Serial Port Connectors (COM1/J41A, COM2–COM5/J2A-D)
- 5.2.5 VMEbus P1 Connector
- 5.2.6 VMEbus P2 Connector
- 5.2.7 MVME721 PMC I/O Module (PIM) Connectors (J10, J14)
- 5.2.8 Planar sATA Power Connector (J30)
- 5.2.9 USB Connector (J27)
- 5.2.10 sATA Connectors (J28 and J29)
- 5.3 Headers
- Memory Maps
- 6.1 Memory Maps
- 6.1.1 Default Processor Memory Map
- 6.1.2 MOTLoad’s Processor Memory Map
- 6.1.3 VME Memory Map
- 6.1.4 System I/O Memory Map
- 6.1.5 System Status Register
- 6.1.6 System Control Register
- 6.1.7 System Indicator Register
- 6.1.8 Flash Control/Status Register
- 6.1.9 PCI Bus Status Registers
- 6.1.10 Interrupt Detect Register
- 6.1.11 Presence Detect Register
- 6.1.12 PLD Revision Register
- 6.1.13 PLD Data Code Register
- 6.1.14 Test Register 1
- 6.1.15 Test Register 2
- 6.1.16 External Timer Registers
- 6.1.17 Geographical Address Register
- 6.1 Memory Maps
- Programming Details
- 7.1 Introduction
- 7.2 MPC8540 Reset Configuration
- 7.3 MPC8540 Interrupt Controller
- 7.4 Local Bus Controller Chip Select Assignments
- 7.5 Two-Wire Serial Interface
- 7.6 User Configuration EEPROM
- 7.7 VPD EEPROM
- 7.8 RTM VPD EEPROM
- 7.9 Ethernet PHY Address
- 7.10 Flash Memory
- 7.11 PCI IDSEL Definition
- 7.12 PCI Arbitration Assignments
- 7.13 Clock Distribution
- 7.14 MPC8540 Real-Time Clock Input
- 7.15 MPC8540 LBC Clock Divisor
- A Specifications
- B Related Documentation
- Safety Notes
- Sicherheitshinweise