Sierra Video Manzanita 321V - Manual (Page 6)

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Sierra Video Systems • P.O. Box 2462 • Grass Valley, CA 95945 • (530) 478-1000 • Fax (530) 478-1105
INSTRUCTION MANUAL
attenuation (over 100db) of an off inputs signal
through the crosspoint. When a crosspoint is on,
both transistors in the signal path are on and the
diode between them is on. Thus the desired video
signal is allowed to pass on to the common bus.
The control of the video crosspoints is done by
four 1 of 8 decoders. A 1 of 4 decoder in turn
enables the proper 1 of 8 decoder. The crosspoint
driving decoders are powered by +8 V and -2 V,
which means that the 31 outputs are at -2V while
the desired crosspoint decoder output is at +8V.
When crosspoint 1 is off, the control side of R4 is
at -2V. Because the anode of D1 is connected to
ground and D1 is in series with R4, their junction
will be at about -0.7V and D1 will be on. The
average voltage at the base of Q1 is 0.0V while its
emitter is at -0.7V. This causes the base emitters
junction of Q1 to be reverse biased and therefore
present a high impedance to the incoming signal
while D1 is a low impedance to the signal. This
produces a fairly high attenuation of the video
signal. Q2, as will be explained later, is also off
and further isolates the input signal when the
crosspoint is in the off state.
To turn on crosspoint one, the first output of the
control decoder changes from -2V to +8. This
causes D1 to now be reverse biased and become a
high impedance. With 0.0V at the base of Q1 and
a positive voltage on R4, Q1 becomes an emitter
follower, buffering the input signal and raising its
DC level to +0.7V. Q2 is another emitter fol-
lower. R13 is its emitter resistor. Q2 lowers the
incoming signal level DC by the same amount it
was raised by Q1. This means the signal DC level
at the common bus of the output of the 16
crosspoints is approximately 0.0V. For an off
crosspoint where D1 is forward biased to -0.7V,
the emitter base junction of Q2 is also reverse
biased by 0.7V. In this way Q2 is used in an off
crosspoint as the second series off switch,
attenuating the input signal.
The output of the 32 crosspoints are divided into
four groups of eight crosspoints each. A diode in
series with each eight crosspoint sub-group helps
to reduce the overall bus capacitance. The output
of the four diodes is tied to a common constant
current configured FET, Q4.
The output circuit, U2, is a 50MHz wideband
video amplifier with a very low output impedance
(about 0.1 ohms). R35, in conjunction with R5 +
variable R4, sets the gain of the entire 503101 to
2X. R21 and R22 raises the output impedance to
75 ohms required to interface to external 75 ohm
coax cable environment.
The output of U2 is also fed to the sync separator
circuit (refer now to sheet 1 of 4 of the schematic
diagram). Q5 is turned on by R19 except during
the negative extreme of sync on the video signal.
This results in 8 V P-P inverted sync at the collector
of Q5. U9A and U9B are connected with R52 and
C9 as a low pass filter which separates vertical
interval from the composite sync output of Q5.
The resulting vertical pulse output of U9D feeds
the IRQ input of the control processor.
The control function for the 503101 is performed
by a single chip microprocessor with internal
program. The Motorola MC68HC711D3, U10,
operates at 1.228MHz (1/4 the 4.9125MHz crystal
oscillator frequency). Remote panel control of the
503101 is by a five wire binary pattern. These
lines are “watched” by U10. When a change in
these lines occurs, U10 waits for vertical interrupt
and then outputs the same pattern on lines PC0
through PC4.
The 5 bit code produced by the PC0-PC4 output
of the processor is decoded by U12 and U3
(repeats 4 times) to drive the 32 individual
crosspoints. Each group of 8 crosspoints is driven
by a 3 line to 8 line decoder (U3). The A, B, C
inputs of the four U3’s are tied in parallel to U10
outputs PC0-PC2. PC3 and PC4 are decoded by
U12, a 2 line to 4 line decoder, to enable the
desired U3 decoder.