Sierra Video Manzanita 321V - Manual (Page 7)

Sierra Video Systems • P.O. Box 2462 • Grass Valley, CA 95945 • (530) 478-1000 • Fax (530) 478-1105
INSTRUCTION MANUAL
7
The 503101 includes the following circuit to
allow for an optional local control panel. The
external 32 switches are connected as an eight by
four matrix to U7 and U6 which provide switch
rollover and convert the switch closure to a five
bit binary code. U4 and U1 do the inverse to drive
the indicator LED’s in the switches which are also
connected as an eight by four matrix.
In addition to remote or local panel control, the
503101 can also be controlled via RS232. The
protocol for this communication appears later in
this manual. The RS232 receive line is converted
to 0 to +5V swings by Q1. The transmit line is
converted from 0 to +5V to +/- 8V by U11.
The 503101 is powered by a 24VAC center
tapped input on J3 pins 27 and 28. This is then
rectified (D8, D9, D10, and 11), filtered (C25 and
C26) and regulated by U14 to +8V, U13 to +5V
and U15 to -8V.
Model 324V Circuit Description
The electronics for the Model 324V are all on a
single plug-in module, the 503130. Refer to the
schematic diagram while reading the following
circuit description.
Each of the 32 video inputs is buffered before
being connected to the crosspoint matrix. The
input buffer consists of Q1 and its associated
components. The buffer performs the following
funtions:
• Provides a high impedance input to the
incoming video signal.
• Provides a low drive impedance to the
crosspoint matrix.
• Raises the signal level one Vbe (0.7V)
to make up for an equal drop in the
crosspoint matrix.
The crosspoint matrix has four identical buses.
Each bus is made up of eight individual 4 by 1 IC
crosspoint switches (U1). To reduce the capacitive
loading effect of eight crosspoint IC’s tied onto a
common bus, the output of each 4 by 1 IC is
connected in series with a diode. The diode has
much lower reverse bias capacitance than the IC
(by about 10 to 1). The +Vbe offset of the input
buffer equals the drop across these diodes, to
return the nominal DC offset to zero.
Each bus is latched and decoded by two IC's. The
latch consists of 5/6th of a 74HC174 hex latch
(U4 typical). U4 outputs are connected back to its
inputs through 22K resistors to form a positive
feedback latch. The clock input to U4 comes from
the Model 324V’s vertical interval clock generator.
The two LSB lines from U4 connect directly to
the A and B inputs of the 8 crosspoint IC’s on
each bus. The three MSB outputs of U4 are
decoded by a 3 to eight decoder, U3 typical. The
desired output of U3 is low and enables the
corresponding 4 by 1 IC crosspoint.
Optional RS232 serial control for the 503130 is
performed by a single chip microprocessor with
internal program. The Motorola MC68HC711D3,
U15, operates at 1.228MHz (1/4 the 4.9125MHz
crystal oscillator frequency). Remote panel con-
trol of the 503130 is by a five wire binary pattern.
These lines are “watched” by U15. When a
change in these lines occurs, U15 sends an update
message out the RS232 port (see Serial Protocol
in the next section of this manual).
When the processor receives a valid serial control
message, the processor drives the proper five
output line with the new crosspoint information
for approximatly 20 milliseonds before returning
those five pins to the input mode.
The 503130 is powered by a 24VAC center
tapped input on J3 pins 27 and 28. This is then
rectified (D2, D3, D4, and D5), filtered (C27 and
C28) and regulated by U12 to +8V, U13 to +5V
and U14 to -8V.