Configuration – Sundance SMT338 User Manual

Page 11

Advertising
background image

Version 1.5

Page 11 of 19

SMT338 User Manual

3. Make sure the that the board is firmly seated, then provide the 3.3V to the board

by screwing the SMT338 on the two main mounting holes with the bolts and
screws provided with the board.

4. Fit the processor-based board on the carrier board. To do so, please follow the

installation procedure of that specific board. In the case of a SMT320 carrier
board, the C4x or C6x board MUST be placed on the first TIM slot (TIM slot 0) of
the SMT320.

5. Connect at least Comm-Port 3 of the SMT338 to one of the transmit Comm-Port

(at Reset) available on the Processor-based board.

6. Connect the SDB links as well if required by your application.
7. Replace the carrier board in the host system.

3. Configuration


The configuration of a SMT338 can only occur when a Global reset has been
asserted to the TIM. The carrier board on which the SMT338 TIM is plugged asserts
its Global Reset, often called TISRESET, at power up or when requested by any
software running on the host (Like Sundance 6000 Server).
The FPGA configuration is done by a software routine running on a host, or a ‘C6x or
‘C4x processor plugged on a carrier board root site.
The Virtex bitstream must be downloaded via Comm-Port 3 of the SMT338 which is
handled by theCPLD. After configuration, the CPLD gives the hand to the FPGA,
which becomes the owner of Comm-Port 3.
The CPLD does the handshake with the Comm-Port and communicates with the
FPGA as well.
The following description is referring to Figure 7.

3.1. Hardware Sequence of events

3.1.1. At power-up.

1) The CPLD polls Comm-Port 3 until it receives the keyword 0xBCBCBCBC.

(WAITFORCMD State)

2) On receiving the start-of-bitstream keyword 0xBCBCBCBC, The CPLD reads out

the FPGA bitstream from Comm-Port 3 and configures the FPGA (CONFIG
State).

3) The FPGA releases its DONE pin when the configuration phase is finished. At

this time LED6 goes on (LED6 is directly driven by DONE). Then, the FPGA
completes its startup sequence and the design downloaded is now ready to start.

Advertising