Sundance SMT399-160 User Manual
User manual
Advertising
Sundance Multiprocessor Technology Limited
Form : QCF42
User Manual
Date : 6 July 2006
Unit / Module Description:
Multi-output DDS based SLB Mezzanine
Unit / Module Number:
SMT399-160
Document Issue Number:
3
Issue Date:
24/05/2007
Original Author:
PSR
User Manual
for
SMT399-160
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor Technology Limited 2006
User Manual SMT399-160
Last Edited: 24/05/2007 17:12:00
Advertising
Table of contents
Document Outline
- 1 Introduction
- 1
- 2 Related Documents
- 1
- 3 Examples of application.
- 4 Functional Description
- 5 Control Register Settings
- 5.1 Control Packet Structure
- 5.2 Reading and Writing Registers
- 5.3 Memory Map
- 5.4 Register Descriptions
- 5.4.1 Reset and Update Register – 0x0.
- 5.4.2 Profile Register – 0x1.
- 5.4.3 VGA0 Register – 0x2.
- 5.4.4 VGA1 Register – 0x3.
- 5.4.5 VGA2 Register – 0x4
- 5.4.6 VGA3 Register – 0x5.
- 5.4.7 DDS0 Register – 0x6 – Control Function Register.
- 5.4.8 DDS0 Register – 0x7 – Control Function Register.
- 5.4.9 DDS0 Register – 0x8 – Control Function Register.
- 5.4.10 DDS0 Register – 0x9 – Amplitude Scale Factor.
- 5.4.11 DDS0 Register – 0xA – Amplitude Ramp Rate.
- 5.4.12 DDS0 Register – 0xB – Frequency Tuning Word 0.
- 5.4.13 DDS0 Register – 0xC – Frequency Tuning Word 0.
- 5.4.14 DDS0 Register – 0xD – Phase Offset Word.
- 5.4.15 DDS0 Register – 0xE – Frequency Tuning Word 1.
- 5.4.16 DDS0 Register – 0xF – Frequency Tuning Word 1.
- 5.4.17 DDS0 Register – 0x10 – RAM Segment Control Word 0.
- 5.4.18 DDS0 Register – 0x11 – RAM Segment Control Word 0.
- 5.4.19 DDS0 Register – 0x12 – RAM Segment Control Word 0.
- 5.4.20 DDS0 Register – 0x13 – RAM Segment Control Word 1.
- 5.4.21 DDS0 Register – 0x14 – RAM Segment Control Word 1.
- 5.4.22 DDS0 Register – 0x15 – RAM Segment Control Word 1.
- 5.4.23 DDS0 Register – 0x16 – RAM Segment Control Word 2.
- 5.4.24 DDS0 Register – 0x17 – RAM Segment Control Word 2.
- 5.4.25 DDS0 Register – 0x18 – RAM Segment Control Word 2.
- 5.4.26 DDS0 Register – 0x19 – RAM Segment Control Word 3.
- 5.4.27 DDS0 Register – 0x1A – RAM Segment Control Word 3.
- 5.4.28 DDS0 Register – 0x1B – RAM Segment Control Word 3.
- 5.4.29 DDS0 Register – 0x1C – Falling Delta Frequency Tuning.
- 5.4.30 DDS0 Register – 0x1D – Falling Delta Frequency Word.
- 5.4.31 DDS0 Register – 0x1E – Falling Sweep Ramp Rate Word.
- 5.4.32 DDS0 Register – 0x1F – Rising Delta Frequency Tuning.
- 5.4.33 DDS0 Register – 0x20 – Rising Delta Frequency Word.
- 5.4.34 DDS0 Register – 0x21 – Rising Sweep Ramp Rate Word.
- 6 PCB Layout
- 7 Connector Location
- 1
- 8 Support Packages
- 1
- 9 Physical Properties
- 10 Safety
- 1
- 11 EMC