Sundance SMT365E - Manual (Page 8)

Version 2.1 Page 8 of 26 SMT365e User Manual
Architecture Description
DSP
The Texas Instruments DSP can run at up to 600MHz. The DSP is doted of 256MB
of Synchronous DRAM (SDRAM).
The DSP is a TMS320C6416 type.
This is a fixed-point digital signal processor provided by Texas Instruments. The
processor will run with zero wait states from internal SRAM. The internal memory is
1MB in size and can be partitioned between normal SRAM and L2 cache.
An on-board crystal oscillator provides the clock used for the DSP which them
multiplies this by twelve internally.
Boot Mode
The DSP is connected to the on-board flash ROM that contains the Sundance
bootloader and the FPGA bitstream.
Following reset, the DSP will automatically load the data from the flash ROM into its
internal program memory at address 0 and then start executing from there. All this
code is the Sundance bootloader, and it is made up of two parts: FPGA configuration
and processor configuration. FPGA configuration uses data in the ROM to configure
the FPGA. A processor configuration sets the processor into a standard state by
writing into the DSP internal registers of the EMIF. Then it configures the FPGA from
the data held in the flash ROM.
The bootloader is executed. It will continually check the six comports until data
appears on one of them. This will next load a program in boot format from this
comport. Note that the bootloader will not read data arriving on other comports.
Finally the control is passed to the loaded DSP application.
The DSP will take approximately about 46s to configure the FPGA following reset,
assuming a 600MHz clock. The external devices implemented in the FPGA (such as
comports) must not be used during this configuration.
It is safest to wait for the configuration to complete. Note that comports will appear to
be "not ready" until the FPGA has been configured.
The FPGA programming algorithm is not described here. It can be found in the boot
code.