Sundance FC202 FPGA - Manual (Page 14)

Sundance Digital Signal Processing Inc. Rev1.0
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: [email protected]
www.sundance.com
4. USAGE
The firmware module is instantiated in a Diamond//FPGA configuration file as follows:
! declare tasks
!
task ogdl ins=1 outs=2 file”..\fc202\fc202.fcd”
!
! place tasks on FPGA
!
place ogdl <fpga>
!
!
!
Connect ? <user_1>[0]
ogdl[0]
Connect ? ogdl[0] <user_2>[0]
Connect ? ogdl[1] <user_2>[1]
Where <user_1> is a data source and <user_2> is a data sink task.
In most cases, it is useful to provide some amount of elastic buffering before and after the
FC202 task in order to help close timings in the FPGA design. This can be accomplished as
follows:
! declare tasks
!
task fifo1 ins=1 outs=1 file”..\fifo\fifo.fcd”
task ogdl ins=1 outs=2 file”..\fc202\fc202.fcd”
task fifo2 ins=1 outs=1 file”..\fifo\fifo.fcd”
task fifo3 ins=1 outs=1 file”..\fifo\fifo.fcd”
!
! place tasks on FPGA
!
place
fifo1 <fpga>
place ogdl <fpga>
place fifo2 <fpga>
place fifo3 <fpga>
!
!
!
Connect
C1 <user_1>[0] fifo1[0]