Sundance FC202 FPGA - Manual (Page 16)

Sundance Digital Signal Processing Inc. Rev1.0
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: [email protected]
www.sundance.com
5. VERFICATION
The firmware module is supported by PARS Test Benches targeted on a mixed DSP + FPGA
module SMT365_8_1, to validate the functionality of the core.
Note: The PARS based verification models generates Diamond configuration files and
applications files. These configuration files can also be used independently without PARS, to
generate Diamond applications. The test benches included under
..\fc202_ea1\test\ will reflect
this in the next release.
DSP Test Bench
A Simulink model of the FC202 core is implemented. The C reference model is generated
using PARS to target the SMT365_8_1 DSP. The Simulink model “fc202_dsp.mdl” is located
under:
..\fc202_ea1\simulink\fc202_dsp\
Note: Please refer to PARS user guide to generate the code to target DSP’s from Simulink
models.
The PARS generated test bench “Subsystem2_TestBench.mdl” is located under
..\fc202_ea1\simulink\fc202_dsp\fc202_dsp_PARS\
Executing the test bench will load the “fc202_dsp_pars.app” into the SMT365_8_1 DSP and
display a scope with the In-phase and Quadrature waveforms of the input samples. Figure 5
below shows the In-Phase and Quadrature waveforms generated by the test bench.
In order to change the Target DSP, a new hardware profile needs to be created in the file
“get_hi.m”. This file is located under PARS directory C:\SundanceDSP\PARS\PARS.
Please refer to PARS user guide for instructions on how to update the “get_hi.m” file.
FPGA Test Bench
A Simulink model “fc202_fpga.mdl” is generated using both Simulink blocks and FC202 core
block. The FC202 block is generated using the “CPBT” utility available under PARS.
The model “fc202_fpga.mdl” is located under