Avago Technologies LSI53C1020 User Manual
Avago Technologies Hardware
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Table of contents
Document Outline
- LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller
- Preface
- Contents
- Chapter1 Introduction
- Chapter2 Functional Description
- Chapter3 Signal Description
- 3.1 Signal Organization
- 3.2 PCI Bus Interface Signals
- 3.3 PCI-Related Signals
- 3.4 SCSI Interface Signals
- 3.5 Memory Interface
- 3.6 Zero Channel RAID (ZCR) Interface
- 3.7 Test Interface
- 3.8 GPIO and LED Signals
- 3.9 Power and Ground Pins
- 3.10 Power-On Sense Pins Description
- 3.11 Internal Pull-Ups and Pull-Downs
- Chapter4 PCI Host Register Description
- 4.1 PCI Configuration Space Register Descriptions
- Table4.1 LSI53C1020 PCI Configuration Space Address Map
- Vendor ID
- Device ID
- Command
- Status
- Revision ID
- Class Code
- Cache Line Size
- Latency Timer
- Header Type
- I/O Base Address
- Memory [0] Low
- Memory [0] High
- Memory [1] Low
- Memory [1] High
- Subsystem Vendor ID
- Subsystem ID
- Expansion ROM Base Address
- Capabilities Pointer
- Interrupt Line
- Interrupt Pin
- Minimum Grant
- Maximum Latency
- Power Management Capability ID
- Power Management Next Pointer
- Power Management Capabilities
- Power Management Control/Status
- Power Management Bridge Support Extensions
- Power Management Data
- MSI Capability ID
- MSI Next Pointer
- Message Control
- Message Address
- Message Upper Address
- Message Data
- PCI-X Capability ID
- PCI-X Next Pointer
- PCI-X Command
- PCI-X Status
- 4.2 I/O Space and Memory Space Register Descriptions
- 4.1 PCI Configuration Space Register Descriptions
- Chapter5 Specifications
- 5.1 DC Characteristics
- Table5.1 Absolute Maximum Stress Ratings
- Table5.2 Operating Conditions
- Table5.3 LVD Driver SCSI Signals – SACK±, SATN±, SBSY±, SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG±,...
- Figure5.1 LVD Driver
- Table5.4 LVD Receiver SCSI Signals – SACK±, SATN±, SBSY±, SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG...
- Figure5.2 LVD Receiver
- Table5.5 DIFFSENS SCSI Signal
- Table5.6 Input Capacitance
- Table5.7 8 mA Bidirectional Signals – GPIO[7:0], MAD[15:0], MADP[1:0], SerialDATA
- Table5.8 8 mA PCI Bidirectional Signals – ACK64/, AD[63:0], C_BE[7:0]/, DEVSEL/, FRAME/, IRDY/, ...
- Table5.9 Input Signals – CLK, DIS_PCI_FSN/, DIS_SCSI_FSN/, GNT/, IDDTN, IDSEL, IOPD_GNT, BZRESET...
- Table5.10 8 mA Output Signals – ALT_INTA/, RAMWE[1:0]/, FLSHALE[1:0]/, FLSHCE/, INTA/, RAMOE/, R...
- Table5.11 12 mA Output Signals – A_LED/, HB_LED/
- 5.2 TolerANT Technology Electrical Characteristics
- 5.3 AC Characteristics
- 5.4 External Memory Timing Diagrams
- 5.5 Pinout Information and Mechanical Drawings
- Figure5.12 LSI53C1020 456-Pin BGA Top View
- Table5.20 LSI53C1020 456-Pin Pinout by Signal Name
- Table5.21 LSI53C1020 456-Pin Pinout by BGA Position
- Figure5.13 LSI53C1020A 384-Pin BGA, Top View
- Table5.22 LSI53C1020A 384-Pin Pinout by Signal Name
- Table5.23 LSI53C1020A 384-Pin Pinout by BGA Position
- Figure5.14 456-Pin EPBGA (KY) Mechanical Drawing
- Figure5.15 384-Ball Count EPBGA (HT) Mechanical Drawing (Sheet 1 of 2)
- Figure5.16 448-Ball Count EPBGA (5B) Mechanical Drawing (Sheet 1 of 2)
- 5.1 DC Characteristics
- AppendixA Register Summary
- Index
- Customer Feedback