Document Outline

• Contents
• Preface
  • About this book
    • Intended audience
    • Using this book
    • Further reading
  • Feedback
    • Feedback on this document
    • Feedback on the Integrator/IM-AD1
• Introduction
  • 1.1 About the Integrator/IM-AD1
  • 1.2 Interface module features and architecture
    • 1.2.1 Features
    • 1.2.2 Architecture
  • 1.3 Links and LEDs
  • 1.4 Care of modules
• Getting Started
  • 2.1 Fitting the interface module
  • 2.2 Setting up the logic module
  • 2.3 Running the test software
• Hardware Reference
  • 3.1 Differences in signal routing between supported logic modules
  • 3.2 UART interface
  • 3.3 SPI
  • 3.4 PWM interface
  • 3.5 Stepper motor interface
    • 3.5.1 Functional description
    • 3.5.2 Stepper motor interface signal summary
    • 3.5.3 Stepper motor connectors
  • 3.6 GPIO
  • 3.7 CAN interface
  • 3.8 ADC and DAC interfaces
• Reference Design Example
  • 4.1 About the design example
    • 4.1.1 About PrimeCells
    • 4.1.2 Example architecture
    • 4.1.3 Example memory map
    • 4.1.4 Address assignment of logic modules
    • 4.1.5 Integrator/IM-AD1 memory map
  • 4.2 Example APB register peripheral
    • 4.2.1 Oscillator divisor registers
    • 4.2.2 Oscillator lock register
    • 4.2.3 User LEDs control register
    • 4.2.4 Push button interrupt register
    • 4.2.5 Switches register
  • 4.3 UART
  • 4.4 SPI chip select register
  • 4.5 Synchronous serial port
  • 4.6 PWM controller
  • 4.7 Stepper motor peripheral
    • 4.7.1 Stepper x control register
    • 4.7.2 Stepx count register
    • 4.7.3 Stepx speed register
  • 4.8 GPIO
    • 4.8.1 Data output set register
    • 4.8.2 Read data input register
    • 4.8.3 Data register output clear
    • 4.8.4 Read data output pins
    • 4.8.5 Data direction
  • 4.9 SSRAM interface
  • 4.10 Vectored interrupt controller
    • 4.10.1 Interrupt sources
  • 4.11 CAN controller interface
    • 4.11.1 CANxBase
    • 4.11.2 CAN reset control register
  • 4.12 ADC and DAC interface
  • 4.13 Peripheral information block
• Signal Descriptions
  • A.1 EXPA
  • A.2 EXPB
  • A.3 EXPIM
  • A.4 Logic analyzer connector
  • A.5 Multi-ICE (JTAG)
• Mechanical Specification
  • B.1 Mechanical information
  • B.2 Connector reference
• Glossary
• Index
  • A
  • B
  • C
  • D
  • E
  • F
  • G
  • I
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • U
  • V