Document Outline

• 1.0 Introduction
  • 1.1 Overview
  • 1.2 Terminology
  • 1.3 Reference Documents
• 2.0 Intel® 82854 GMCH Overview
  • 2.1 System Architecture
    • 2.1.1 Intel® 82854 GMCH
  • 2.2 Processor Host Interface
  • 2.3 GMCH System Memory Interface
  • 2.4 Graphics Features
  • 2.5 Display Features
    • 2.5.1 GMCH Analog Display Port
    • 2.5.2 GMCH Integrated DVO Ports
  • 2.6 Hub Interface
  • 2.7 Address Decode Policies
  • 2.8 GMCH Clocking
  • 2.9 System Interrupts
• 3.0 Signal Description
  • 3.1 Host Interface Signals
  • 3.2 DDR SDRAM Interface
  • 3.3 Hub Interface Signals
  • 3.4 Clocks
  • 3.5 Internal Graphics Display Signals
    • 3.5.1 Digital Video Output B (DVOB) Port
    • 3.5.2 Digital Video Output C (DVOC) Port
    • 3.5.3 Analog CRT Display
    • 3.5.4 General Purpose Input/Output Signals
  • 3.6 Voltage References, PLL Power
• 4.0 Register Description
  • 4.1 Conceptual Overview of the Platform Configuration Structure
  • 4.2 Nomenclature for Access Attributes
  • 4.3 Standard PCI Bus Configuration Mechanism
  • 4.4 Routing Configuration Accesses
    • 4.4.1 PCI Bus #0 Configuration Mechanism
    • 4.4.2 Primary PCI and Downstream Configuration Mechanism
  • 4.5 Register Definitions
  • 4.6 I/O Mapped Registers
    • 4.6.1 CONFIG_ADDRESS - Configuration Address Register
    • 4.6.2 CONFIG_DATA - Configuration Data Register
  • 4.7 VGA I/O Mapped Registers
  • 4.8 Intel 854 GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0)
    • 4.8.1 VID - Vendor Identification Register
    • 4.8.2 DID - Device Identification Register
    • 4.8.3 PCICMD - PCI Command Register
    • 4.8.4 PCI Status Register
    • 4.8.5 RID - Register Identification
    • 4.8.6 SUBC - Sub Class Code Register
    • 4.8.7 BCC - Base Class Code Register
    • 4.8.8 HDR - Header Type Register
    • 4.8.9 SVID - Subsystem Vendor Identification Register
    • 4.8.10 SID - Subsystem Identification Register
    • 4.8.11 CAPPTR - Capabilities Pointer Register
    • 4.8.12 CAPID - Capabilities Identification Register (Device #0)
    • 4.8.13 GMC - GMCH Miscellaneous Control Register (Device #0)
    • 4.8.14 GGC - GMCH Graphics Control Register (Device #0)
    • 4.8.15 DAFC - Device and Function Control Register (Device #0)
    • 4.8.16 FDHC - Fixed DRAM Hold Control Register (Device #0)
    • 4.8.17 PAM(6:0) - Programmable Attribute Map Register (Device #0)
    • 4.8.18 SMRAM - System Management RAM Control Register (Device #0)
    • 4.8.19 ESMRAMC - Extended System Management RAM Control (Device #0)
    • 4.8.20 ERRSTS - Error Status Register (Device #0)
    • 4.8.21 ERRCMD - Error Command Register (Device #0)
    • 4.8.22 SMICMD - SMI Error Command Register (Device #0)
    • 4.8.23 SCICMD - SCI Error Command Register (Device #0)
    • 4.8.24 SHIC - Secondary Host Interface Control Register (Device #0)
    • 4.8.25 HEM - Host Error Control, Status, and Observation (Device #0)
  • 4.9 Intel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)
    • 4.9.1 VID - Vendor Identification Register
    • 4.9.2 DID - Device Identification Register
    • 4.9.3 PCICMD - PCI Command Register
    • 4.9.4 PCISTS - PCI Status Register
    • 4.9.5 RID - Revision Identification Register
    • 4.9.6 RID - Revision Identification Register
    • 4.9.7 BCC - Base Class Code Register
    • 4.9.8 HDR - Header Type Register
    • 4.9.9 SVID - Subsystem Vendor Identification Register
    • 4.9.10 SID - Subsystem Identification Register
    • 4.9.11 CAPPTR - Capabilities Pointer Register
    • 4.9.12 DRB - DRAM Row (0:3) Boundary Register (Device #0)
    • 4.9.13 DRA - DRAM Row Attribute Register (Device #0)
    • 4.9.14 DRT - DRAM Timing Register (Device #0)
    • 4.9.15 PWRMG - DRAM Controller Power Management Control Register (Device #0)
    • 4.9.16 DRC - DRAM Controller Mode Register (Device #0)
    • 4.9.17 DTC - DRAM Throttling Control Register (Device #0)
  • 4.10 Intel 854 GMCH Configuration Process Registers (Device #0, Function #3)
    • 4.10.1 VID - Vendor Identification Register
    • 4.10.2 DID - Device Identification Register
    • 4.10.3 PCICMD - PCI Command Register
    • 4.10.4 PCISTS - PCI Status Register
    • 4.10.5 RID - Revision Identification Register
    • 4.10.6 SUBC - Sub-Class Code Register
    • 4.10.7 BCC - Base Class Code Register
    • 4.10.8 HDR - Header Type Register
    • 4.10.9 SVID - Subsystem Vendor Identification Register
    • 4.10.10 ID - Subsystem Identification Register
    • 4.10.11 CAPPTR - Capabilities Pointer Register
    • 4.10.12 HPLLCC - HPLL Clock Control Register (Device #0)
  • 4.11 Intel® 82854 GMCH Integrated Graphics Device Registers (Device #2, Function #0)
    • 4.11.1 VID - Vendor Identification Register (Device #2)
    • 4.11.2 DID - Device Identification Register (Device #2)
    • 4.11.3 PCICMD - PCI Command Register (Device #2)
    • 4.11.4 PCISTS - PCI Status Register (Device #2)
    • 4.11.5 RID - Revision Identification Register (Device #2)
    • 4.11.6 CC - Class Code Register (Device #2)
    • 4.11.7 CLS - Cache Line Size Register (Device #2)
    • 4.11.8 MLT - Master Latency Timer Register (Device #2)
    • 4.11.9 HDR - Header Type Register (Device #2)
    • 4.11.10 GMADR - Graphics Memory Range Address Register (Device #2)
    • 4.11.11 MMADR - Memory Mapped Range Address Register (Device #2)
    • 4.11.12 IOBAR - I/O Base Address Register (Device #2)
    • 4.11.13 SVID - Subsystem Vendor Identification Register (Device #2)
    • 4.11.14 SID - Subsystem Identification Register (Device #2)
    • 4.11.15 ROMADR - Video BIOS ROM Base Address Registers (Device #2)
    • 4.11.16 INTRLINE - Interrupt Line Register (Device #2)
    • 4.11.17 INTRPIN - Interrupt Pin Register (Device #2)
    • 4.11.18 MINGNT - Minimum Grant Register (Device #2)
    • 4.11.19 MAXLAT - Maximum Latency Register (Device #2)
    • 4.11.20 PMCAP - Power Management Capabilities Register (Device #2)
    • 4.11.21 PMCS - Power Management Control/Status Register (Device #2)
• 5.0 Intel® 82854 GMCH System Address Map
  • 5.1 System Memory Address Ranges
  • 5.2 DOS Compatibility Area
  • 5.3 Extended System Memory Area
  • 5.4 Main System Memory Address Range (0010_0000h to Top of Main Memory)
    • 5.4.1 15 MB-16 MB Window
    • 5.4.2 Pre-allocated System Memory
    • 5.4.3 System Management Mode (SMM) Memory Range
    • 5.4.4 System Memory Shadowing
    • 5.4.5 I/O Address Space
    • 5.4.6 GMCH Decode Rules and Cross-Bridge Address Mapping
    • 5.4.7 Hub Interface Decode Rules
• 6.0 Functional Description
  • 6.1 Host Interface Overview
  • 6.2 Dynamic Bus Inversion
    • 6.2.1 System Bus Interrupt Delivery
    • 6.2.2 Upstream Interrupt Messages
  • 6.3 System Memory Interface
    • 6.3.1 DDR SDRAM Interface Overview
    • 6.3.2 System Memory Organization and Configuration
    • 6.3.3 DDR SDRAM Performance Description
  • 6.4 Integrated Graphics Overview
    • 6.4.1 3D/2D Instruction Processing
    • 6.4.2 3D Engine
    • 6.4.3 Raster Engine
    • 6.4.4 2D Engine
    • 6.4.5 Planes and Engines
    • 6.4.6 Hardware Cursor Plane (Native Graphic Mode only)
    • 6.4.7 Overlay Plane
    • 6.4.8 Video Functionality
  • 6.5 Internal Graphic Display Interface
    • 6.5.1 Pipe A Timing Generator Unit
    • 6.5.2 Blend Function
    • 6.5.3 Interlaced Video Field display
    • 6.5.4 Interlace support for Video Overlay Window
    • 6.5.5 Analog Display Port Characteristics
• 7.0 Power and Thermal Management
  • 7.1 General Description of Supported CPU States
  • 7.2 General Description of ACPI States
  • 7.3 Internal Thermal Sensor
    • 7.3.1 Overview
    • 7.3.2 Hysteresis Operation
  • 7.4 External Thermal Sensor Input
    • 7.4.1 Usage
• 8.0 Intel® 82854 GMCH Strap Pins
  • 8.1 Strapping Configuration
• 9.0 Ballout and Package Information
  • 9.1 VCC/VSS Voltage Groups
  • 9.2 Package Mechanical Information