0 register description, Register description, 15 device number assignment – Intel D15343-003 User Manual

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Register Description

D15343-003

41

4.0

Register Description

4.1

Conceptual Overview of the Platform Configuration
Structure

The GMCH and ICH4-M are physically connected by a Hub interface. From a configuration
standpoint, the Hub interface is logically PCI bus #0. As a result, all devices internal to the GMCH
and ICH4-M appear to be on PCI bus #0. The system's primary PCI expansion bus is physically
attached to the ICH4-M and from a configuration perspective, appears to be a hierarchical PCI bus
behind a PCI-to-PCI bridge and therefore has a programmable PCI Bus number. Note that the
primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a
configuration standpoint. For the GMCH, the graphics subsystem appears to system software to be
a real PCI bus behind PCI-to-PCI bridges, resident as devices on PCI bus #0.

The GMCH contains two PCI devices within a single physical component. The configuration
registers for the two devices are mapped as devices residing on PCI bus #0.

Device #0: Host-Hub Interface Bridge/DDR SDRAM Controller. Logically this appears as a PCI
device residing on PCI bus #0. Physically, Device #0 contains the standard PCI registers, DDR
SDRAM registers, the Graphics Aperture Controller registers, HI Control registers and other
GMCH specific registers. Device #0 is divided into the following functions:

Function #0: Host Bridge Legacy registers including Graphics Aperture Control registers, HI
Configuration registers and Interrupt Control registers

Function #1: DDR SDRAM Interface Registers

Function #3: Intel Configuration Process Registers

Device #2: Integrated Graphics Controller. Logically this appears as a PCI device residing on PCI
bus #0. Physically Device #2 contains the Configuration registers for 2D, 3D, and display
functions.

Note:

The legacy VGA registers are only supported when the Intel

®

82854 GMCH is strapped into

Native Graphics Mode.

Table 15

shows the Device # assignment for the various internal GMCH devices.

Table 15.

Device Number Assignment

GMCH Function

Bus #0, Device#

Host-Hub interface, DDR SDRAM I/F, Legacy control

Device #0

Integrated Graphics Controller (IGD)

Device #2

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