Intel D15343-003 User Manual
Intel
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Table of contents
Document Outline
- 1.0 Introduction
- 2.0 Intel® 82854 GMCH Overview
- 3.0 Signal Description
- 4.0 Register Description
- 4.1 Conceptual Overview of the Platform Configuration Structure
- 4.2 Nomenclature for Access Attributes
- 4.3 Standard PCI Bus Configuration Mechanism
- 4.4 Routing Configuration Accesses
- 4.5 Register Definitions
- 4.6 I/O Mapped Registers
- 4.7 VGA I/O Mapped Registers
- 4.8 Intel 854 GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0)
- 4.8.1 VID - Vendor Identification Register
- 4.8.2 DID - Device Identification Register
- 4.8.3 PCICMD - PCI Command Register
- 4.8.4 PCI Status Register
- 4.8.5 RID - Register Identification
- 4.8.6 SUBC - Sub Class Code Register
- 4.8.7 BCC - Base Class Code Register
- 4.8.8 HDR - Header Type Register
- 4.8.9 SVID - Subsystem Vendor Identification Register
- 4.8.10 SID - Subsystem Identification Register
- 4.8.11 CAPPTR - Capabilities Pointer Register
- 4.8.12 CAPID - Capabilities Identification Register (Device #0)
- 4.8.13 GMC - GMCH Miscellaneous Control Register (Device #0)
- 4.8.14 GGC - GMCH Graphics Control Register (Device #0)
- 4.8.15 DAFC - Device and Function Control Register (Device #0)
- 4.8.16 FDHC - Fixed DRAM Hold Control Register (Device #0)
- 4.8.17 PAM(6:0) - Programmable Attribute Map Register (Device #0)
- 4.8.18 SMRAM - System Management RAM Control Register (Device #0)
- 4.8.19 ESMRAMC - Extended System Management RAM Control (Device #0)
- 4.8.20 ERRSTS - Error Status Register (Device #0)
- 4.8.21 ERRCMD - Error Command Register (Device #0)
- 4.8.22 SMICMD - SMI Error Command Register (Device #0)
- 4.8.23 SCICMD - SCI Error Command Register (Device #0)
- 4.8.24 SHIC - Secondary Host Interface Control Register (Device #0)
- 4.8.25 HEM - Host Error Control, Status, and Observation (Device #0)
- 4.9 Intel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)
- 4.9.1 VID - Vendor Identification Register
- 4.9.2 DID - Device Identification Register
- 4.9.3 PCICMD - PCI Command Register
- 4.9.4 PCISTS - PCI Status Register
- 4.9.5 RID - Revision Identification Register
- 4.9.6 RID - Revision Identification Register
- 4.9.7 BCC - Base Class Code Register
- 4.9.8 HDR - Header Type Register
- 4.9.9 SVID - Subsystem Vendor Identification Register
- 4.9.10 SID - Subsystem Identification Register
- 4.9.11 CAPPTR - Capabilities Pointer Register
- 4.9.12 DRB - DRAM Row (0:3) Boundary Register (Device #0)
- 4.9.13 DRA - DRAM Row Attribute Register (Device #0)
- 4.9.14 DRT - DRAM Timing Register (Device #0)
- 4.9.15 PWRMG - DRAM Controller Power Management Control Register (Device #0)
- 4.9.16 DRC - DRAM Controller Mode Register (Device #0)
- 4.9.17 DTC - DRAM Throttling Control Register (Device #0)
- 4.10 Intel 854 GMCH Configuration Process Registers (Device #0, Function #3)
- 4.10.1 VID - Vendor Identification Register
- 4.10.2 DID - Device Identification Register
- 4.10.3 PCICMD - PCI Command Register
- 4.10.4 PCISTS - PCI Status Register
- 4.10.5 RID - Revision Identification Register
- 4.10.6 SUBC - Sub-Class Code Register
- 4.10.7 BCC - Base Class Code Register
- 4.10.8 HDR - Header Type Register
- 4.10.9 SVID - Subsystem Vendor Identification Register
- 4.10.10 ID - Subsystem Identification Register
- 4.10.11 CAPPTR - Capabilities Pointer Register
- 4.10.12 HPLLCC - HPLL Clock Control Register (Device #0)
- 4.11 Intel® 82854 GMCH Integrated Graphics Device Registers (Device #2, Function #0)
- 4.11.1 VID - Vendor Identification Register (Device #2)
- 4.11.2 DID - Device Identification Register (Device #2)
- 4.11.3 PCICMD - PCI Command Register (Device #2)
- 4.11.4 PCISTS - PCI Status Register (Device #2)
- 4.11.5 RID - Revision Identification Register (Device #2)
- 4.11.6 CC - Class Code Register (Device #2)
- 4.11.7 CLS - Cache Line Size Register (Device #2)
- 4.11.8 MLT - Master Latency Timer Register (Device #2)
- 4.11.9 HDR - Header Type Register (Device #2)
- 4.11.10 GMADR - Graphics Memory Range Address Register (Device #2)
- 4.11.11 MMADR - Memory Mapped Range Address Register (Device #2)
- 4.11.12 IOBAR - I/O Base Address Register (Device #2)
- 4.11.13 SVID - Subsystem Vendor Identification Register (Device #2)
- 4.11.14 SID - Subsystem Identification Register (Device #2)
- 4.11.15 ROMADR - Video BIOS ROM Base Address Registers (Device #2)
- 4.11.16 INTRLINE - Interrupt Line Register (Device #2)
- 4.11.17 INTRPIN - Interrupt Pin Register (Device #2)
- 4.11.18 MINGNT - Minimum Grant Register (Device #2)
- 4.11.19 MAXLAT - Maximum Latency Register (Device #2)
- 4.11.20 PMCAP - Power Management Capabilities Register (Device #2)
- 4.11.21 PMCS - Power Management Control/Status Register (Device #2)
- 5.0 Intel® 82854 GMCH System Address Map
- 6.0 Functional Description
- 7.0 Power and Thermal Management
- 8.0 Intel® 82854 GMCH Strap Pins
- 9.0 Ballout and Package Information