Document Outline

• Intel® IQ80333 I/O Processor
• Introduction 1
  • 1.1 Document Purpose and Scope
  • 1.2 Other Related Documents
    • Table 1. Intel® 80333 I/O Processor Related Documentation List
  • 1.3 Electronic Information
    • Table 2. Electronic Information
  • 1.4 Component References
    • Table 3. Component Reference
  • 1.5 Terms and Definitions
    • Table 4. Terms and Definitions
  • 1.6 Intel® 80333 I/O Processor
    • Figure 1. Intel® 80333 I/O Processor Block Diagram
  • 1.7 Intel® IQ80333 I/O Processor Evaluation Platform Board Features
    • Table 5. Summary of Features
• Getting Started 2
  • 2.1 Kit Content
  • 2.2 Hardware Installation
    • 2.2.1 First-Time Installation and Test
    • 2.2.2 Power Requirements
  • 2.3 Factory Settings
  • 2.4 Development Strategy
    • 2.4.1 Supported Tool Buckets
    • 2.4.2 Contents of the Flash
  • 2.5 Target Monitors
    • 2.5.1 RedHat RedBoot
  • 2.6 Host Communications Examples
    • 2.6.1 Serial-UART Communication
      • Figure 2. Serial-UART Communication
    • 2.6.2 JTAG Debug Communication
      • Figure 3. JTAG Debug Communication
    • 2.6.3 Network Communication
      • Figure 4. Network Communication Example
    • 2.6.4 GNUPro GDB/Insight
      • 2.6.4.1 Communicating with RedBoot
      • 2.6.4.2 Connecting with GDB
• Hardware Reference Section 3
  • 3.1 Functional Diagram
    • Figure 5. Intel® 80333 I/O Processor Functional Block Diagram
  • 3.2 Board Form-Factor/Connectivity
    • Table 6. Form-Factor/Connectivity Features
    • Figure 6. Board Form Factor
  • 3.3 Power
    • Table 7. Power Features
  • 3.4 Memory Subsystem
    • 3.4.1 DDR SDRAM
      • 3.4.1.1 Battery Backup
    • 3.4.2 Flash Memory Requirements
      • Table 8. Flash Memory Requirements
  • 3.5 Interrupt Routing
    • Table 9. External Interrupt Routing to Intel® 80333 I/O Processor
  • 3.6 Intel® IQ80333 I/O Processor Evaluation Platform Board Peripheral Bus
    • Figure 7. Intel® IQ80333 I/O Processor Evaluation Platform Board Peripheral Bus Topology
    • Table 10. Peripheral Bus Features
    • 3.6.1 Flash ROM
      • Table 11. Flash ROM Features
      • Figure 8. Flash Connection on Peripheral Bus
    • 3.6.2 UART
    • 3.6.3 Non-Volatile RAM
    • 3.6.4 Audio Buzzer
    • 3.6.5 HEX Display
    • 3.6.6 Rotary Switch
      • Table 12. Rotary Switch Requirements
    • 3.6.7 Battery Status
      • Table 13. Battery Status Buffer Requirements
  • 3.7 Debug Interface
    • 3.7.1 Console Serial Port
    • 3.7.2 JTAG Debug
      • 3.7.2.1 JTAG Port
        • Figure 9. JTAG Port Pin-out
  • 3.8 Board Reset Scheme
    • Table 14. Reset Requirements/Schemes
    • Figure 10. RESET Sources
  • 3.9 Switches and Jumpers
    • 3.9.1 Switch Summary
      • Table 15. Switch Summary
    • 3.9.2 Default Switch Settings of S7A1- Visual
      • Table 16. Switch S7A1
      • Figure 11. Default Switch Setting Switch S7A1
    • 3.9.3 Jumper Summary
      • Table 17. Jumper Summary
    • 3.9.4 Connector Summary
      • Table 18. Connector Summary
    • 3.9.5 General Purpose Input/Output Header
      • Table 19. J2D2 GPIO Header Definition
    • 3.9.6 Detail Descriptions of Switches/Jumpers
      • 3.9.6.1 Switch S1C2: Intel® 80333 I/O Processor Reset
      • 3.9.6.2 Switch S6A1: BPCI-X Reset
      • 3.9.6.3 Switch S8A1: Rotary
        • Table 20. Rotary Switch Settings
      • 3.9.6.4 Switch S7A1
        • 3.9.6.4.1 S7A1-1: PCI-X Bus A Speed Enable Corresponding to Signal Name PBI_AD3
          • Table 21. S7A1-1: PCI-X Bus A Speed Enable
        • 3.9.6.4.2 S7A1-2: Reset I/O Processor Core Corresponding to Signal Name PBI_AD5
          • Table 22. Switch S7A1-2: Reset IOP: Settings and Operation Mode
        • 3.9.6.4.3 S7A1-3: Configration Cycle Enable Corresponding to Signal Name PBI_AD6
          • Table 23. Switch S7A1-3: RETRY: Settings and Operation Mode
        • 3.9.6.4.4 S7A1-4: PCI-X Bus B Speed Enable Corresponding to Signal Name PBI_AD10
          • Table 24. S7A1-4: PCI-X Bus B Speed Enable: Settings and Operation Mode
        • 3.9.6.4.5 S7A1-5: PCI-X Bus B Hot-Plug Reset Disable Corresponding to Signal Name PBI_AD11
          • Table 25. S7A1-5: PCI-X Bus B Hot-Plug Reset Disable: Settings and Operation Mode
        • 3.9.6.4.6 Switch S7A1- 6: Hot Plug Capable Disabled Corresponding to Signal Name PBI_AD15
          • Table 26. Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode
        • 3.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 Corresponding to Signal Name PBI_AD17
          • Table 27. Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode
        • 3.9.6.4.8 Switch S7A1 - 8: SMBUS Manageability Address Bit 3 Corresponding to Signal Name PBI_AD18
          • Table 28. Switch S7A1 - 8: SMBUS Manageability Address Bit 3: Settings and Operation Mode
        • 3.9.6.4.9 Switch S7A1- 9:SMBUS Manageability Address Bit 2 Corresponding to Signal Name PBI_AD17
          • Table 29. Switch S7A1 - 9: SMBUS Manageability Address Bit 2: Settings and Operation Mode
        • 3.9.6.4.10 Switch S7A1- 10: SMBUS Manageability Address Bit 1 Corresponding to Signal Name PBI_AD16
          • Table 30. Switch S7A1 - 10: SMBUS Slave Address 0: Settings and Operation Mode
      • 3.9.6.5 Jumper J7D1: Flash bit-width
        • Table 31. Jumper J7D1: Descriptions
        • Table 32. Jumper J7D1: Settings and Operation Mode
      • 3.9.6.6 Jumper J1C1: JTAG Chain
        • Table 33. Jumper J1C1: Descriptions
        • Table 34. Jumper J1C1: Settings and Operation Mode
      • 3.9.6.7 Jumper J1D2: UART Control
        • Table 35. Jumper J1D2: Descriptions
        • Table 36. Jumper J1D2: Settings and Operation Mode
      • 3.9.6.8 Jumper J7B4: SMBus Header
        • Table 37. Jumper J7B4: Descriptions
        • Table 38. Jumper J7B4: Settings and Operation Mode
      • 3.9.6.9 Jumper J9D3: Buzzer Volume Control
        • Table 39. Jumper J9D3: Descriptions
        • Table 40. Jumper J9D3: Settings and Operation Mode
• Software Reference 4
  • 4.1 DRAM
  • 4.2 Components on the Peripheral Bus
    • 4.2.1 Flash ROM
      • Figure 12. Flash Connection to Peripheral Bus
    • 4.2.2 Peripheral Bus Memory Map
      • Table 41. Peripheral Bus Memory Map
  • 4.3 Board Support Package (BSP) Examples
    • 4.3.1 Intel® 80333 I/O Processor Memory Map
      • Figure 13. Intel® 80333 I/O Processor Memory Map
    • 4.3.2 RedBoot* Intel® 80333 I/O Processor Memory Map
    • 4.3.3 RedBoot Intel® 80333 I/O Processor Files
    • 4.3.4 RedBoot Intel® 80332 I/O Processor DDR Memory Initialization Sequence
• IQ80321 and IQ80333 Comparisons A
  • Table 42. Intel® IQ80321 Evaluation Platform Board and Intel® IQ80333 I/O Processor Evaluation Platform Board Comparisons
• Getting Started and Debugger B
  • B.1 Introduction
    • B.1.1 Purpose
    • B.1.2 Necessary Hardware and Software
    • B.1.3 Related Documents
      • Table 43. Related Documents
    • B.1.4 Related Web Sites
  • B.2 Setup
    • B.2.1 Hardware Setup
      • Figure 14. Intel® 80333 I/O Processor Hardware Setup Flow Chart
    • B.2.2 Software Setup
      • Figure 15. Software Flow Diagram
  • B.3 New Project Setup
    • B.3.1 Creating a New Project
    • B.3.2 Configuration
  • B.4 Flashing with JTAG
    • B.4.1 Overview
    • B.4.2 Using Flash Programmer
  • B.5 Debugging Out of Flash
  • B.6 Building an Executable File From Example Code
  • B.7 Running the Code|Lab Debugger
    • B.7.1 Launching and Configuring Debugger
    • B.7.2 Manually Loading and Executing an Application Program
    • B.7.3 Displaying Source Code
    • B.7.4 Using Breakpoints
    • B.7.5 Stepping Through the Code
    • B.7.6 Setting Code|Lab Debug Options
  • B.8 Exploring the Code|Lab Debug Windows
    • B.8.1 Toolbar Icons
    • B.8.2 Workspace Window
    • B.8.3 Source Code
    • B.8.4 4 Debug and Console Windows
    • B.8.5 Memory Window
    • B.8.6 Registers Window
    • B.8.7 Watch Window
    • B.8.8 Variables Window
  • B.9 Debugging Basics
    • B.9.1 Overview
    • B.9.2 Hardware and Software Breakpoints
      • B.9.2.1 Software Breakpoints
      • B.9.2.2 Hardware Breakpoints
    • B.9.3 Exceptions/Trapping