Intel IQ80333 User Manual
Intel
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Table of contents
Document Outline
- Intel® IQ80333 I/O Processor
- Introduction 1
- Getting Started 2
- Hardware Reference Section 3
- 3.1 Functional Diagram
- 3.2 Board Form-Factor/Connectivity
- 3.3 Power
- 3.4 Memory Subsystem
- 3.5 Interrupt Routing
- 3.6 Intel® IQ80333 I/O Processor Evaluation Platform Board Peripheral Bus
- 3.7 Debug Interface
- 3.8 Board Reset Scheme
- 3.9 Switches and Jumpers
- 3.9.1 Switch Summary
- 3.9.2 Default Switch Settings of S7A1- Visual
- 3.9.3 Jumper Summary
- 3.9.4 Connector Summary
- 3.9.5 General Purpose Input/Output Header
- 3.9.6 Detail Descriptions of Switches/Jumpers
- 3.9.6.1 Switch S1C2: Intel® 80333 I/O Processor Reset
- 3.9.6.2 Switch S6A1: BPCI-X Reset
- 3.9.6.3 Switch S8A1: Rotary
- 3.9.6.4 Switch S7A1
- 3.9.6.4.1 S7A1-1: PCI-X Bus A Speed Enable Corresponding to Signal Name PBI_AD3
- 3.9.6.4.2 S7A1-2: Reset I/O Processor Core Corresponding to Signal Name PBI_AD5
- 3.9.6.4.3 S7A1-3: Configration Cycle Enable Corresponding to Signal Name PBI_AD6
- 3.9.6.4.4 S7A1-4: PCI-X Bus B Speed Enable Corresponding to Signal Name PBI_AD10
- 3.9.6.4.5 S7A1-5: PCI-X Bus B Hot-Plug Reset Disable Corresponding to Signal Name PBI_AD11
- 3.9.6.4.6 Switch S7A1- 6: Hot Plug Capable Disabled Corresponding to Signal Name PBI_AD15
- 3.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 Corresponding to Signal Name PBI_AD17
- 3.9.6.4.8 Switch S7A1 - 8: SMBUS Manageability Address Bit 3 Corresponding to Signal Name PBI_AD18
- 3.9.6.4.9 Switch S7A1- 9:SMBUS Manageability Address Bit 2 Corresponding to Signal Name PBI_AD17
- 3.9.6.4.10 Switch S7A1- 10: SMBUS Manageability Address Bit 1 Corresponding to Signal Name PBI_AD16
- 3.9.6.5 Jumper J7D1: Flash bit-width
- 3.9.6.6 Jumper J1C1: JTAG Chain
- 3.9.6.7 Jumper J1D2: UART Control
- 3.9.6.8 Jumper J7B4: SMBus Header
- 3.9.6.9 Jumper J9D3: Buzzer Volume Control
- Software Reference 4
- IQ80321 and IQ80333 Comparisons A
- Getting Started and Debugger B