Document Outline

• TABLE OF CONTENTS
• SECTION 1: OVERVIEW
• SECTION 2: ARCHITECTURE
  • 2.1 Overview
    • 2.1.1 References
    • 2.1.2 Instruction Set
    • 2.1.3 Harvard Memory Archite...
    • 2.1.4 Register Space
  • 2.2 Architecture
    • 2.2.1 Instruction Decoding
    • 2.2.2 Register Space
    • 2.2.3 Memory Organization
      • 2.2.3.1 Program Memory
      • 2.2.3.2 Utility ROM
      • 2.2.3.3 Data Memory
      • 2.2.3.4 Stack Memory
      • 2.2.3.5 Pseudo-Von Neumann M...
      • 2.2.3.6 Pseudo-Von Neumann M...
      • 2.2.3.7 Data Alignment
      • 2.2.3.8 Memory Management Unit
    • 2.2.4 Interrupts
      • 2.2.4.1 Servicing Interrupts
      • 2.2.4.2 Interrupt System Ope...
      • 2.2.4.3 Synchronous vs. Asyn...
      • 2.2.4.4 Interrupt Prioritiza...
      • 2.2.4.5 Interrupt Exception ...
      • 2.2.4.6 MAXQ7667 Interrupt S...
• SECTION 3: PROGRAMMING
  • 3.1 Addressing Modes
  • 3.2 Prefixing Operations
  • 3.3 Reading and Writing Regi...
    • 3.3.1 Loading an 8-Bit Regis...
    • 3.3.2 Loading a 16-Bit Regis...
    • 3.3.3 Moving Values Between ...
    • 3.3.4 Moving Values Between ...
      • 3.3.4.1 8-Bit Destination ¨ ...
      • 3.3.4.2 8-Bit Destination ¨ ...
      • 3.3.4.3 16-Bit Destination ¨...
      • 3.3.4.4 Low (16-Bit Destinat...
      • 3.3.4.5 High (16-Bit Destina...
  • 3.4 Reading and Writing Regi...
  • 3.5 Using the Arithmetic and...
    • 3.5.1 Selecting the Active A...
    • 3.5.2 Enabling Autoincrement...
    • 3.5.3 ALU Operations Using t...
    • 3.5.4 ALU Operations Using O...
    • 3.5.5 ALU Bit Operations Usi...
    • 3.5.6 Example: Adding Two 4-...
  • 3.6 Processor Status Flag Op...
    • 3.6.1 Sign Flag
    • 3.6.2 Zero Flag
    • 3.6.3 Equals Flag
    • 3.6.4 Carry Flag
    • 3.6.5 Overflow Flag
  • 3.7 Controlling Program Flow
    • 3.7.1 Obtaining the Next Exe...
    • 3.7.2 Unconditional Jumps
    • 3.7.3 Conditional Jumps
    • 3.7.4 Calling Subroutines
    • 3.7.5 Looping Operations
    • 3.7.6 Conditional Returns
  • 3.8 Handling Interrupts
    • 3.8.1 Conditional Return fro...
  • 3.9 Accessing the Stack
  • 3.10 Accessing Data Memory
• SECTION 4: REGISTER DESCRIPTIONS
  • 4.1 System Register Descript...
    • 4.1.1 Accumulator Pointer Re...
    • 4.1.2 Accumulator Pointer Co...
    • 4.1.3 Processor Status Flags...
    • 4.1.4 Interrupt and Control ...
    • 4.1.5 Interrupt Mask Registe...
    • 4.1.6 System Control Registe...
    • 4.1.7 Interrupt Identificati...
    • 4.1.8 System Clock Control R...
    • 4.1.9 Watchdog Timer Control...
    • 4.1.10 Accumulator n Registe...
    • 4.1.11 Prefix Register (PFX[n])
    • 4.1.12 Instruction Pointer R...
    • 4.1.13 Stack Pointer Registe...
    • 4.1.14 Interrupt Vector Regi...
    • 4.1.15 Loop Counter 0 Regist...
    • 4.1.16 Loop Counter 1 Regist...
    • 4.1.17 Frame Pointer Offset ...
    • 4.1.18 Data Pointer Control ...
    • 4.1.19 General Register (GR)
    • 4.1.20 General Register Low ...
    • 4.1.21 Frame Pointer Base Re...
    • 4.1.22 General Register Byte...
    • 4.1.23 General Register High...
    • 4.1.24 General Register Sign...
    • 4.1.25 Frame Pointer Registe...
    • 4.1.26 Data Pointer 0 Regist...
    • 4.1.27 Data Pointer 1 Regist...
  • 4.2 Peripheral Register Modules
• SECTION 5: GENERAL-PURPOSE I/O MODULE
  • 5.1 Architecture
    • 5.1.1 Enhanced Type D I/O Port
    • 5.1.2 GPIO Port Pins
  • 5.2 Port Registers
    • 5.2.1 Port 0 Output Register...
    • 5.2.2 Port 1 Output Register...
    • 5.2.3 External Interrupt Fla...
    • 5.2.4 External Interrupt Fla...
    • 5.2.5 Port 0 Input Register ...
    • 5.2.6 Port 1 Input Register ...
    • 5.2.7 External Interrupt Ena...
    • 5.2.8 External Interrupt Ena...
    • 5.2.9 Port 0 Direction Regis...
    • 5.2.10 Port 1 Direction Regi...
    • 5.2.11 External Interrupt Ed...
    • 5.2.12 External Interrupt Ed...
    • 5.2.13 Pad Drive Strength Re...
    • 5.2.14 Pad Drive Strength Re...
    • 5.2.15 Pad Resistive Pull Di...
    • 5.2.16 Pad Resistive Pull Di...
  • 5.3 GPIO Operation
    • 5.3.1 Port Direction Control...
    • 5.3.2 Port P0 and P1 Externa...
    • 5.3.3 Port Pin Special and A...
    • 5.3.4 Port Pin Examples
      • 5.3.4.1 Port Pin Example 1: ...
      • 5.3.4.2 Port Pin Example 2: ...
• SECTION 6: TYPE 2 TIMER/COUNTER MODULE
  • 6.1 Architecture
    • 6.1.1 Modes of Operation for...
    • 6.1.2 Type 2 Timer/Counter I...
  • 6.2 Type 2 Timer/Counter Per...
  • 6.3 Type 2 Status/Control Re...
    • 6.3.1 Type 2 Timer/Counter C...
    • 6.3.2 Type 2 Timer/Counter C...
    • 6.3.3 Type 2 Timer/Counter C...
  • 6.4 Type 2 Counter Registers
    • 6.4.1 Type 2 Timer/Counter V...
    • 6.4.2 Type 2 Timer/Counter V...
  • 6.5 Type 2 Reload Register
    • 6.5.1 Type 2 Timer/Counter R...
    • 6.5.2 Type 2 Timer/Counter R...
  • 6.6 Type 2 Capture/Compare R...
    • 6.6.1 Type 2 Timer/Counter C...
    • 6.6.2 Type 2 Timer/Counter C...
  • 6.7 Type 2 Timer/Counter Ope...
    • 6.7.1 16-Bit Timer: Autorelo...
    • 6.7.2 16-Bit Timer: Capture ...
    • 6.7.3 16-Bit Counter
    • 6.7.4 Dual 8-Bit Timers
    • 6.7.5 8-Bit Timer/8-Bit Capt...
    • 6.7.6 8-Bit Timer/8-Bit Counter
    • 6.7.7 Type 2 Timer Input Clo...
    • 6.7.8 Type 2 Timer Compare A...
      • 6.7.8.1 A Simple Waveform Ou...
      • 6.7.8.2 Waveform Output with...
    • 6.7.9 Type 2 Timer Capture A...
      • 6.7.9.1 Measure Low-Pulse Du...
      • 6.7.9.2 Measure High-Pulse D...
      • 6.7.9.3 Measure Period
      • 6.7.9.4 Measure Duty Cycle R...
      • 6.7.9.5 Overflow/Interrupt o...
• SECTION 7: SCHEDULE TIMER
  • 7.1 Architecture
  • 7.2 Schedule Timer Register ...
    • 7.2.1 Schedule Timer Control...
    • 7.2.2 Schedule Timer Registe...
    • 7.2.3 Schedule Alarm Registe...
  • 7.3 Schedule Timer Operation
• SECTION 8: UART AND LIN
  • 8.1 Architecture
  • 8.2 UART/LIN Pins
  • 8.3 UART and LIN Register De...
    • 8.3.1 Control Register 1 (UA...
    • 8.3.2 Serial Control Registe...
    • 8.3.3 Serial Port Buffer Reg...
    • 8.3.4 FIFO Status Register (...
    • 8.3.5 Error Register (UART) ...
    • 8.3.6 Checksum Register (UAR...
    • 8.3.7 Interrupt State Vector...
    • 8.3.8 Status Register 0 (UAR...
    • 8.3.9 Serial Mode Register (...
    • 8.3.10 FIFO Control Register...
    • 8.3.11 Control Register 0 (U...
    • 8.3.12 Control Register 2 (U...
    • 8.3.13 Identifier Boundary R...
    • 8.3.14 Serial Address Regist...
    • 8.3.15 Serial Address Mask R...
    • 8.3.16 Bit Timing Register (...
    • 8.3.17 Timer Register (UART)...
  • 8.4 MAXQ7667 LIN
    • 8.4.1 MAXQ7667 LIN Features
    • 8.4.2 LIN Frame
    • 8.4.3 LIN Peripheral
    • 8.4.4 LIN Master
      • 8.4.4.1 LIN Master Setup Exa...
      • 8.4.4.2 LIN Master Sending P...
      • 8.4.4.3 LIN Master Polling f...
      • 8.4.4.4 LIN Master Setup to ...
    • 8.4.5 LIN Slave
      • 8.4.5.1 LIN Slave Setup Example
      • 8.4.5.2 LIN Slave Receiving ...
      • 8.4.5.3 LIN Slave Polling fo...
      • 8.4.5.4 LIN Slave Setup to T...
      • 8.4.5.5 LIN Slave Setup to T...
    • 8.4.6 Receive Filter
    • 8.4.7 Identifier Boundary Re...
    • 8.4.8 LIN Transmit and Recei...
    • 8.4.9 Setting LIN Baud Rate
    • 8.4.10 LIN Interrupts
      • 8.4.10.1 LIN Interrupt Example
      • 8.4.10.2 LIN Master/Slave In...
    • 8.4.11 Power Features
    • 8.4.12 LIN Error Handling
  • 8.5 MAXQ7667 UART
    • 8.5.1 MAXQ7667 UART Features
    • 8.5.2 MAXQ7667 UART Modes
      • 8.5.2.1 UART Mode 0
      • 8.5.2.2 UART Mode 1
      • 8.5.2.3 UART Mode 2
      • 8.5.2.4 UART Mode 3
    • 8.5.3 Framing Error Detection
    • 8.5.4 UART Mode 1 Asynchrono...
    • 8.5.5 UART Interrupts Example
    • 8.5.6 UART Transmit Data Exa...
    • 8.5.7 UART Receive Data Example
    • 8.5.8 Setting UART Baud Rate
    • 8.5.9 UART FIFO
• SECTION 9: ENHANCED SERIAL PERIPHERAL INTERFACE (SPI) MODULE
  • 9.1 Architecture
    • 9.1.1 SPI Status and Control...
      • 9.1.1.1 SPI Data Buffer Regi...
      • 9.1.1.2 SPI Control Register...
      • 9.1.1.3 SPI Configuration Re...
      • 9.1.1.4 SPI Clock Register (...
    • 9.1.2 Master Mode
    • 9.1.3 Slave Mode
    • 9.1.4 SPI Clocking Modes
    • 9.1.5 Baud-Rate Determination
    • 9.1.6 Data Format
  • 9.2 SPI Port Errors
    • 9.2.1 Receive Overrun Flag (...
    • 9.2.2 Write Collision Flag (...
    • 9.2.3 Mode Fault Flag (MODF)
  • 9.3 SPI Interrupts
  • 9.4 Resetting the SPI Port
  • 9.5 Oscillator/Clock Power-S...
    • 9.5.1 Stop Mode
• SECTION 10: HARDWARE MULTIPLIER MODE
  • 10.1 Hardware Multiplier Org...
  • 10.2 Hardware Multiplier Per...
    • 10.2.1 Hardware Multiplier C...
    • 10.2.2 Multiplier Operand A ...
    • 10.2.3 Multiplier Operand B ...
    • 10.2.4 Multiplier Accumulato...
    • 10.2.5 Multiplier Accumulato...
    • 10.2.6 Multiplier Accumulato...
    • 10.2.7 Multiplier Read Regis...
    • 10.2.8 Multiplier Read Regis...
  • 10.3 Hardware Multiplier Con...
  • 10.4 Register Output Selection
  • 10.5 Signed-Unsigned Operand...
  • 10.6 Operand Count Selection
  • 10.7 Hardware Multiplier Ope...
  • 10.8 Accessing the Multiplier
  • 10.9 MAXQ7667 Hardware Multi...
• SECTION 11: TEST ACCESS PORT (TAP)
  • 11.1 TAP Overview
  • 11.2 Architecture
    • 11.2.1 TAP Pins
  • 11.3 TAP Interface Control
    • 11.3.1 System Control Regist...
  • 11.4 TAP Controller Operation
    • 11.4.1 Communication via TAP
    • 11.4.2 Test-Logic-Reset
    • 11.4.3 Run-Test-Idle
    • 11.4.4 IR-Scan Sequence
    • 11.4.5 DR-Scan Sequence
    • 11.4.6 TAP Communication Exa...
• SECTION 12: IN-CIRCUIT DEBUG MODE
  • 12.1 Architecture
  • 12.2 In-Circuit Debug Periph...
    • 12.2.1 In-Circuit Debug Temp...
    • 12.2.2 In-Circuit Debug Temp...
    • 12.2.3 In-Circuit Debug Cont...
    • 12.2.4 In-Circuit Debug Flag...
    • 12.2.5 In-Circuit Debug Buff...
    • 12.2.6 In-Circuit Debug Addr...
    • 12.2.7 In-Circuit Debug Data...
    • 12.2.8 System Control Regist...
  • 12.3 Debug Engine Operation
    • 12.3.1 Background Mode Opera...
    • 12.3.2 Breakpoint Registers
      • 12.3.2.1 Breakpoint Register...
      • 12.3.2.2 Breakpoint Register...
      • 12.3.2.3 Breakpoint Register...
    • 12.3.3 Using Breakpoints
    • 12.3.4 Debug Mode
    • 12.3.5 Debug Mode Commands
    • 12.3.6 Read-Register Map Com...
    • 12.3.7 Single-Step (Trace) O...
    • 12.3.8 Return
    • 12.3.9 Debug Mode Special Co...
    • 12.3.10 Debug Command Operation
      • 12.3.10.1 Register Read and ...
      • 12.3.10.2 Data Memory Read C...
      • 12.3.10.3 Data Memory Write ...
      • 12.3.10.4 Program Stack Read...
      • 12.3.10.5 Read Register Map ...
• SECTION 13: IN-SYSTEM PROGRAMMING/BOOTLOADER
  • 13.1 Bootstrap-Loader Mode
  • 13.2 In-System Programming P...
    • 13.2.1 In-Circuit Debug Flag...
    • 13.2.2 System Control Regist...
  • 13.3 Bootloader Protocol
    • 13.3.1 Family 0 Commands (No...
    • 13.3.2 Family 1 Commands: Lo...
    • 13.3.3 Family 2 Commands: Du...
    • 13.3.4 Family 3 Commands: CR...
    • 13.3.5 Family 4 Commands: Ve...
    • 13.3.6 Family 5 Commands: Lo...
    • 13.3.7 Family 6 Commands: Er...
    • 13.3.8 Family E Commands: Er...
  • 13.4 Password-Protected Access
    • 13.4.1 Entering a Password
  • 13.5 JTAG Bootloader Operation
  • 13.6 UART Bootloader Operation
    • 13.6.1 UART Bootloader Host ...
• SECTION 14: SAR ADC MODULE
  • 14.1 Architecture
  • 14.2 SAR ADC Pins
  • 14.3 SAR ADC Registers
    • 14.3.1 SAR ADC Control Regis...
    • 14.3.2 Analog Interrupt Enab...
    • 14.3.3 Analog Status Registe...
    • 14.3.4 SAR ADC Output Data R...
    • 14.3.5 Oscillator Control Re...
    • 14.3.6 Analog Power Enable R...
  • 14.4 Voltage References
  • 14.5 Analog-to-Digital Conve...
    • 14.5.1 Single-Ended/Differen...
    • 14.5.2 True Differential Ana...
    • 14.5.3 Unipolar/Bipolar
    • 14.5.4 Transfer Function
    • 14.5.5 Analog Input Protection
    • 14.5.6 ADC Clock
    • 14.5.7 Auto Shutdown Mode
    • 14.5.8 ADC Conversion Start ...
    • 14.5.9 ADC Interrupts
    • 14.5.10 Using the ADC
    • 14.5.11 Measuring ADC Refere...
• SECTION 15: OSCILLATOR/CLOCK GENERATION
  • 15.1 Architecture
  • 15.2 Oscillator/Clock Status...
    • 15.2.1 Analog Interrupt Enab...
    • 15.2.2 Analog Status Registe...
    • 15.2.3 Oscillator Control Re...
    • 15.2.4 System Clock Control ...
    • 15.2.5 Watchdog Timer Contro...
    • 15.2.6 RC Oscillator Trim Re...
  • 15.3 System Clock Generation
    • 15.3.1 Internal RC Oscillator
      • 15.3.1.1 Recalibrating the R...
    • 15.3.2 External Oscillator a...
    • 15.3.3 Internal System Clock...
  • 15.4 External Oscillator Clo...
  • 15.5 Watchdog Timer
  • 15.6 Oscillator/Clock Power-...
    • 15.6.1 Stop Mode
      • 15.6.1.1 Resuming from Stop ...
    • 15.6.2 Switchback Mode
• SECTION 16: POWER-SUPPLY/SUPERVISORY MONITORING
  • 16.1 Power-Supply/Supervisor...
  • 16.2 Power-Supply/Supervisor...
    • 16.2.1 Analog Interrupt Enab...
    • 16.2.2 Analog Status Registe...
    • 16.2.3 Analog Power Enable R...
    • 16.2.4 Watchdog Timer Contro...
  • 16.3 Supply Configuration
    • 16.3.1 5V Regulator with Ext...
      • 16.3.1.1 Depletion Mode FET ...
      • 16.3.1.2 Darlington Bipolar ...
      • 16.3.1.3 Enhancement Mode FE...
  • 16.4 Power-On Reset
    • 16.4.1 Reset Output
  • 16.5 Power-Supply Voltage Mo...
    • 16.5.1 Digital Core Supply (...
    • 16.5.2 Digital I/O Supply (D...
    • 16.5.3 Analog Supply Voltage...
  • 16.6 Reset Mode
    • 16.6.1 Watchdog Timer Reset
    • 16.6.2 External Reset
    • 16.6.3 Internal System Reset
• SECTION 17: ULTRASONIC DISTANCE MEASUREMENT MODULE--BURST TRANSMISSION AND ECHO RECEPTION
  • 17.1 Architecture
    • 17.1.1 Burst Transmission Stage
    • 17.1.2 Echo Reception
  • 17.2 Burst Transmission and ...
  • 17.3 Echo Burst Transmission...
    • 17.3.1 Burst Pulse-Width Hig...
    • 17.3.2 Burst Transmit Contro...
    • 17.3.3 Echo Path Control Reg...
    • 17.3.4 PLL-Based Programmabl...
    • 17.3.5 Analog Interrupt Enab...
    • 17.3.6 Echo Envelope Compara...
    • 17.3.7 Echo Envelope Compara...
    • 17.3.8 Analog Status Registe...
    • 17.3.9 Echo Envelope Lowpass...
    • 17.3.10 Echo Envelope Bandpa...
    • 17.3.11 Echo Envelope Bandpa...
    • 17.3.12 Echo Envelope Lowpas...
    • 17.3.13 Echo Envelope Lowpas...
    • 17.3.14 Analog Power Enable ...
  • 17.4 Burst Signal Generation
    • 17.4.1 Setting Up the Hardware
      • 17.4.1.1 External RC Filter ...
      • 17.4.1.2 Ultrasonic Transducer
    • 17.4.2 Setting Up the Regist...
      • 17.4.2.1 Turning On the PLL ...
      • 17.4.2.2 Configuring the Bur...
      • 17.4.2.3 Triggering the Burs...
    • 17.4.3 Burst Generation Example
  • 17.5 Echo Reception
    • 17.5.1 Hardware Setup
      • 17.5.1.1 Receiver Clock Freq...
      • 17.5.1.2 Voltage Reference f...
      • 17.5.1.3 External Input Coup...
    • 17.5.2 Software Setup
      • 17.5.2.1 Powering Up Receive...
      • 17.5.2.2 Echo Receive Regist...
    • 17.5.3 Echo Receive Data Reg...
• SECTION 18: UTILITY ROM
  • 18.1 In-Application Programm...
  • 18.2 Data Transfer Functions
  • 18.3 ROM Example 1: Calling ...
  • 18.4 ROM Example 2: Calling ...
• SECTION 19: INSTRUCTION SET SUMMARY
  • ADD/ADDC src
  • AND src
  • AND Acc.<b>
  • {L/S}CALL
  • CMP src
  • CPL
  • CPL C
  • {L/S}DJNZ LC[n], src
  • {L/S}JUMP src
  • {L/S}JUMP C/{L/S}JUMP NC, sr...
  • MOVE dst, src
  • MOVE Acc.<b>, C
  • MOVE C, Acc.<b>
  • MOVE C, src.<b>
  • MOVE C, #0
  • MOVE C, #1
  • MOVE dst.<b>, #0
  • MOVE dst.<b>, #1
  • NEG
  • OR src
  • OR Acc.<b>
  • POP dst
  • POPI dst
  • PUSH src
  • RET
  • RET C/RET NC, RET Z/RET NZ, ...
  • RETI
  • RETI C/RETI NC, RETI Z/RETI ...
  • RL/RLC
  • RR/RRC
  • SLA/SLA2/SLA4
  • SR/SRA/SRA2/SRA4
  • SUB/SUBB src
  • XCH
  • XCHN
  • XOR src
  • XOR Acc.<b>
• REVISION HISTORY