Maxim Integrated MAXQ7667 - Manual (Page 153)

8.4.9 Setting LIN Baud Rate
The LIN baud rate is set using the BT register. The LIN master uses the baud-rate bit timing when it issues a break/sync sequence.
The LIN slave captures the sync timing and set its BT to match the master’s.
To set the LIN baud rate the following formula is used:
BT = System Clock/LIN Baud Rate
For example, for the LIN baud rate of 20kBd, with a 16MHz crystal as the clock source.
BT = (16MHz/20kHz) ≥ 800 ≥ 0x0320
The BT register is then loaded with 0x0320, which sets the LIN communication speed for 20kBd.
8.4.10 LIN Interrupts
After the LIN controller has been set up, the ISVEC register can be used to monitor the state of the LIN controller. To use the interrupts,
the global, Module 3, and LIN interrupts need to be enabled. Once enabled, the ISVEC register interrupt is used to determine the LIN
status. After the status is determined, an interrupt service routine (ISR) can take the appropriate action. The following steps are used
to enable the LIN interrupts.
• Set the interrupt global enable (IGE) bit in the Interrupt Control (IC) register.
• Set the interrupt mask 3 (IM3) bit in the Interrupt Mask (IMR) register.
• Set the interrupt enable (INE) bit in the CNT0 register.
Once the interrupts have been enabled for LIN, the ISVEC register contains the priority encoded interrupt vector states as shown in
Table 8-3 ( Note that the highest priority is 0 and the lowest priority is 15.) The application software should monitor the ISVEC states
for LIN status and take action if necessary.
8.4.10.1 LIN Interrupt Example
See the following example on how to use the ISVEC register in an ISR. This example assumes an interrupt is caused by LIN and deter-
mines the status from the ISVEC register.
• Clear the interrupt ID 3 (II3) bit in the Interrupt Identification (IIR) register.
• Preserve the ISVEC register by copying it to another variable such as ISV_Test.
• Test the ISV_Test variable to see which condition from Table 8-3 caused the interrupt.
• Take the appropriate action to resolve the interrupt cause.
8.4.10.2 LIN Master/Slave Interrupt Example
In the following example, flags are used for the LIN master and slave examples mentioned previously. The ISR sets a flag when the
transmission or reception of data is complete.
• Test the ISV_Test variable and if ISV_Test = 2, either receive or transmit complete.
• If LIN set for slave (CNT0 bits LUN = 2), set RX_OK = 1.
• If LIN set for master (CNT0 bits LUN = 3), set TX_OK = 1.
8.4.11 Power Features
To reduce the power, the system clock can be removed by placing the MAXQ7667 in stop mode. To place the MAXQ7667 in stop mode,
the CKCN register bit STOP is written.
The MAXQ7667 has internal circuitry to detect activity on the LIN bus and wake up from either of the low-power modes. To enable the
wake-up circuitry, the wake-up bit (WU) in CNT0 is set to detect activity on the LIN bus. In addition, an interrupt can occur by setting
the power management (PM) bit in CNT2.
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MAXQ7667 User’s Guide