Maxim Integrated MAXQ7667 - Manual (Page 170)

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MAXQ7667 User’s Guide
Bit 5: Receive Overrun Flag (ROVR). This flag detects if a received character was lost because a previous piece of data had not
been read out of the SPIB register. The data in the SPI port shift register is overrun and lost. This bit is read- and write-access enabled
and can be set by individual bit write operations.
0 = No receive overrun has occurred.
1 = Receive overrun occurred.
Bit 4: Write Collision Flag (WCOL). This flag detects a write to the SPIB register, while the port is shifting out data from a previous
operation. If a transfer is in progress (STBY = 1), an attempt to write the SPIB sets the WCOL flag, and the operation is ignored so as
not to corrupt the contents of the SPIB. Accesses to the SPIB are only allowed when the STBY flag is 0. All forms of reset clear this bit.
Writing a 0 to it also clears the bit. This bit is read- and write-access enabled and can be set by individual bit write operations.
0 = No write collision has been detected.
1 = Write collision detected.
Bit 3: Mode-Fault Flag (MODF). This bit is the mode-fault flag for SPI master mode operation. A mode fault occurs when the SS line
is asserted (0) on a device that is configured in SPI master mode. When mode-fault detection is enabled (MODFE = 1) in master mode,
detection of a high-to-low transition on the SS pin signifies a mode fault. All forms of reset clear this bit. Writing a 0 to this bit also clear
it. This bit is read- and write-access enabled and can be set by individual bit write operations.
0 = No mode fault has been detected.
1 = Mode fault detected while operating as a master (MSTM = 1).
Bit 2: Mode-Fault Enable (MODFE). When MODFE is set to logic 1, the SS input pin is enabled to detect a mode fault during SPI mas-
ter mode operation. A mode fault occurs when the SS line is asserted (0) on a device that is configured in master mode. When this bit
is programmed to 0, mode-fault detection is disabled. All forms of reset clear this bit. This bit is read- and write-access enabled and
can be set by individual bit write operations.
Bit 1: Master Mode Enable (MSTM). The MSTM bit functions as the master mode enable bit for the SPI module. Note that this bit can
only be set if the SPI port is inactive and SS is deasserted. All forms of reset clear this bit. A mode-fault condition also clears this bit if
the mode-fault-enable bit is set. This bit is read- and write-access enabled and can be set by individual bit write operations.
0 = SPI module operates in slave mode.
1 = SPI module operates in master mode.
Bit 0: SPI Enable (SPIEN). The SPIEN bit enables the SPI port for operation. All forms of reset clear this bit. The bit is also cleared on
a mode-fault condition if the mode-fault-enable bit is set. This bit is read- and write-access enabled and can be set by individual bit
write operations.
0 = SPI module and the baud-rate generator are disabled.
1 = SPI module and the baud-rate generator are enabled.