Maxim Integrated MAXQ7667 - Manual (Page 174)

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MAXQ7667 User’s Guide
Data can be written to the serial register once the STBY flag is cleared and the SPIC flag is set. This allows the next transfer to begin
while the read operation is pending. In this overlapped mode, the read buffer must be emptied before the next character is complete-
ly loaded into the shift register. Should the next transfer cycle complete, the ROVR flag is set if the SPIB contents have not been read.
Figure 9-3 shows a typical master mode transfer cycle with SPIB read and write cycles.
Figure 9-3. Master Mode Transfer Cycle Operation
SYSCLK
SPIB WRITE
FLAG CLEARED UNDER
SOFTWARE CONTROL
TRANSFER
COMPLETE
DATA WRITTEN
INTO READ BUFFER
SLAVE
DISABLE
STBY FLAG
SPIC FLAG
SPIB READ
SPICK (CKPOL = 0)
(CKPHA = 0)
SAMPLE EDGE SHIFT EDGE
SPICK (CKPOL = 1)
(CKPHA = 0)
MOSI
MISO
SS
MSB 6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB MSB
SLAVE
ENABLE