Document Outline

• BLOCK DIAGRAMS
• APPLICATIONS
• FEATURE DETAILS
  • Global Features
  • Receive DS3/E3 LIU Features
  • Jitter Attenuator Features
  • Receive DS3/E3 Framer Features
  • Transmit DS3/E3 Formatter Features
  • Transmit DS3/E3 LIU Features
  • Clock Rate Adapter Features
  • HDLC Controller Features
  • FEAC Controller Features
  • Trail Trace Buffer Features
  • Bit Error-Rate Tester (BERT) Features
  • Loopback Features
  • Microprocessor Interface Features
  • Slave Serial Peripheral Interface (SPI) Features
  • Test Features
• STANDARDS COMPLIANCE
• ACRONYMS AND GLOSSARY
• MAJOR OPERATIONAL MODES
  • DS3/E3 Framed LIU Mode
  • DS3/E3 Unframed LIU Mode
  • DS3/E3 Framed POS/NEG Mode
  • DS3/E3 Unframed POS/NEG Mode
  • DS3/E3 Framed UNI Mode
  • DS3/E3 Unframed UNI Mode
• PIN DESCRIPTIONS
  • Short Pin Descriptions
  • Detailed Pin Descriptions
  • Pin Functional Timing
    • Line IO
      • B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing
      • B3ZS/HDB3/AMI Mode Receive Pin Functional Timing
      • UNI Mode Transmit Pin Functional Timing
      • UNI Mode Receive Pin Functional Timing
    • DS3/E3 Framing Overhead Functional Timing
    • DS3/E3 Serial Data Interface
      • DS3/E3 Framed Mode Transmit Serial Interface Pin Functional Timing
      • DS3/E3 Framed Mode Receive Serial Interface Pin Functional Timing
    • Microprocessor Interface Functional Timing
      • SPI Functional Timing Diagrams
        • SPI Transmission Format and CPHA Polarity
      • Parallel Port Interface Diagrams
    • JTAG Functional Timing
• INITIALIZATION AND CONFIGURATION
  • Monitoring and Debugging
• FUNCTIONAL DESCRIPTION
  • Processor Bus Interface
    • SPI Serial Port Mode
    • 8/16 Bit Bus Widths
    • Ready Signal (RDY)
    • Byte Swap Modes
    • Read-Write/Data Strobe Modes
    • Clear on Read/Clear on Write Modes
    • Interrupt and Pin Modes
    • Interrupt Structure
  • Clocks
    • Line Clock Modes
      • Loop Timing Enabled
        • LIU Enabled, Loop Timing Enabled
        • LIU Disabled, Loop Timing Enabled
      • Loop Timing Disabled
        • LIU Enabled - CLAD Timing Disabled – no LB
        • LIU Enabled - CLAD Timing Enabled – no LB
        • LIU Disabled - CLAD Timing Disabled – no LB
        • LIU Disabled - CLAD Timing Enabled – no LB
    • Sources of Clock Output Pin Signals
    • Line IO Pin Timing Source Selection
      • Transmit Line Interface Pins Timing Source Selection
      • Transmit Framer Pin Timing Source Selection
      • Receive Line Interface Pin Timing Source Selection
      • Receiver Framer Pin Timing Source Selection
    • Clock Structures On Signal IO Pins
    • Gapped Clocks
  • Reset and Power-Down
  • Global Resources
    • Clock Rate Adapter (CLAD)
    • 8 kHz Reference Generation
    • One Second Reference Generation
    • General-Purpose IO Pins
    • Performance Monitor Counter Update Details
    • Transmit Manual Error Insertion
  • Port Resources
    • Loopbacks
      • Analog Loopback (ALB)
      • Line Loopback (LLB)
      • Payload Loopback (PLB)
      • Diagnostic Loopback (DLB)
    • Loss Of Signal Propagation
    • AIS Logic
    • Loop Timing Mode
    • HDLC Overhead Controller
    • Trail Trace
    • BERT
    • System Port Pins
      • Transmit System Port Pins
      • Receive System Port Pins
    • Framing Modes
    • Line Interface Modes
  • DS3/E3 Framer / Formatter
    • General Description
    • Features
      • Transmit Formatter
      • Receive Framer
    • Transmit Formatter
    • Receive Framer
      • • Receive DS3 Framing
        • Receive DS3 Performance Monitoring
    • C-bit DS3 Framer/Formatter
      • Transmit C-bit DS3 Frame Processor
      • Transmit C-bit DS3 Frame Generation
      • Transmit C-bit DS3 Error Insertion
      • Transmit C-bit DS3 Overhead Insertion
      • Transmit C-bit DS3 AIS/Idle Generation
        • Receive C-bit DS3 Frame Format
        • Receive C-bit DS3 Overhead Extraction
    • M23 DS3 Framer/Formatter
      • Transmit M23 DS3 Frame Processor
      • Transmit M23 DS3 Frame Generation
      • Transmit M23 DS3 Error Insertion
      • Transmit M23 DS3 Overhead Insertion
      • Transmit M23 DS3 AIS/Idle Generation
        • Receive M23 DS3 Frame Format
        • Receive M23 DS3 Overhead Extraction
        • Receive DS3 Downstream AIS Generation
    • G.751 E3 Framer/Formatter
      • Transmit G.751 E3 Frame Processor
      • Transmit G.751 E3 Frame Generation
      • Transmit G.751 E3 Error Insertion
      • Transmit G.751 E3 Overhead Insertion
      • Transmit G.751 E3 AIS Generation
      • Receive G.751 E3 Frame Processor
        • Receive G.751 E3 Framing
        • Receive G.751 E3 Performance Monitoring
        • Receive G.751 E3 Overhead Extraction
        • Receive G.751 Downstream AIS Generation
    • G.832 E3 Framer/Formatter
      • Transmit G.832 E3 Frame Processor
      • Transmit G.832 E3 Frame Generation
      • Transmit G.832 E3 Error Insertion
      • Transmit G.832 E3 Overhead Insertion
      • Transmit G.832 E3 AIS Generation
      • Receive G.832 E3 Frame Processor
      • Receive G.832 E3 Framing
      • Receive G.832 E3 Performance Monitoring
      • Receive G.832 E3 Overhead Extraction
      • Receive G.832 Downstream AIS Generation
  • HDLC Overhead Controller
    • General Description
    • Features
    • Transmit FIFO
    • Transmit HDLC Overhead Processor
    • Receive HDLC Overhead Processor
    • Receive FIFO
  • Trail Trace Controller
    • General Description
    • Features
    • Functional Description
    • Transmit Data Storage
    • Transmit Trace ID Processor
    • Transmit Trail Trace Processing
    • Receive Trace ID Processor
    • Receive Trail Trace Processing
    • Receive Data Storage
  • FEAC Controller
    • General Description
    • Features
    • Functional Description
      • Transmit Data Storage
      • Transmit FEAC Processor
      • Receive FEAC Processor
      • Receive FEAC FIFO
  • Line Encoder/Decoder
    • General Description
    • Features
    • B3ZS/HDB3 Encoder
    • Transmit Line Interface
    • Receive Line Interface
    • B3ZS/HDB3 Decoder
  • BERT
    • General Description
    • Features
    • Configuration and Monitoring
    • Receive Pattern Detection
      • Receive PRBS Synchronization
      • Receive Repetitive Pattern Synchronization
      • Receive Pattern Monitoring
    • Transmit Pattern Generation
      • Transmit Error Insertion
  • LIU – Line Interface Unit
    • General Description
    • Features
      • Transmitter
      • Receiver
    • Detailed Description
    • Transmitter
      • Transmit Clock
      • Waveshaping, Line Build-Out, Line Driver
      • Interfacing to the Line
      • Transmit Driver Monitor
      • Transmitter Power-Down
      • Transmitter Jitter Generation (Intrinsic)
      • Transmitter Jitter Transfer
    • Receiver
      • Interfacing to the Line
      • Optional Preamp
      • Automatic Gain Control (AGC) and Adaptive Equalizer.
      • Clock and Data Recovery (CDR)
      • Loss-of-Signal (LOS) Detector
      • Receiver Power-Down
      • Receiver Jitter Tolerance.
• OVERALL REGISTER MAP
• REGISTER MAPS AND DESCRIPTIONS
  • Registers Bit Maps
    • Global Register Bit Map
    • HDLC Register Bit Map
    • T3 Register Bit Map
    • E3 G.751 Register Bit Map
    • E3 G.832 Register Bit Map
  • Global Registers
    • Register Bit Descriptions
  • Port Register
    • Register Bit Descriptions
  • BERT
    • BERT Register Map
    • BERT Register Bit Descriptions
  • B3ZS/HDB3 Line Encoder/Decoder
    • Transmit Side Line Encoder/Decoder Register Map
      • Register Bit Descriptions
    • Receive Side Line Encoder/Decoder Register Map
      • Register Bit Descriptions
  • HDLC
    • HDLC Transmit Side Register Map
      • Register Bit Descriptions
    • HDLC Receive Side Register Map
      • Register Bit Descriptions
  • FEAC Controller
    • FEAC Transmit Side Register Map
      • Register Bit Descriptions
    • FEAC Receive Side Register Map
      • Register Bit Descriptions
  • Trail Trace
    • Trail Trace Transmit Side
      • Register Bit Descriptions
    • Trail Trace Receive Side Register Map
      • Register Bit Descriptions
  • DS3/E3 framer
    • Transmit DS3
      • Register Bit Descriptions
    • Receive DS3 Register Map
      • Register Bit Descriptions
    • Transmit G.751 E3
      • Register Map
      • Register Bit Descriptions
    • Receive G.751 E3 Register Map
      • Register Bit Descriptions
    • Transmit G.832 E3 Register Map
      • Register Bit Descriptions
    • Receive G.832 E3 Register Map
      • Register Bit Descriptions
• JTAG INFORMATION
  • JTAG Description
  • JTAG TAP Controller State Machine Description
  • JTAG Instruction Register and Instructions
  • JTAG ID Codes
  • JTAG Functional Timing
  • IO Pins
• PIN CONFIGURATIONS
• PACKAGE INFORMATION
• PACKAGE THERMAL INFORMATION
• DC ELECTRICAL CHARACTERISTICS
• AC TIMING CHARACTERISTICS
  • Framer Data Path AC Characteristics
  • Overhead Port AC Characteristics
  • Micro Interface AC Characteristics
    • SPI Bus Mode
    • Parallel Bus Mode
  • CLAD Jitter Characteristics
  • LIU Interface AC Characteristics
    • Waveform Templates
    • LIU Input/Output Characteristics
  • JTAG Interface AC Characteristics
• REVISION HISTORY