Rainbow Electronics DS3170 - Manual (Page 117)

DS3170 DS3/E3 Single-Chip Transceiver
117 of 233
10 OVERALL REGISTER MAP
The register addresses of the global, test and the port are concatenated to cover the address range of 000 to 7FF.
The address map requires 9 bits of address, ADR[8:0].
The register banks that are not marked with an “X” are not writeable and read back all zeroes. Bits that are
underlined are read-only; all other bits are read-write.
Unused bits and registers marked with “—“ are ignored when written to, and return zero when read.
Configuration registers can be written to and read from during a data path reset ( DRST low, and RST high).
However, all changes to these registers will be ignored during the data path reset. As a result, all initiating action
requiring a “0 to 1” transition must be re-initiated after the data path reset is released.
All counters saturate at their maximum count. A counter register is updated by asserting (low to high transition) the
performance monitoring update signal (PMU). During the counter register update process, the performance
monitoring status signal (PMS) will be deasserted. The counter register update process consists of loading the
counter register with the current count, resetting the counter, forcing the zero count status indication low for one
clock period, and then asserting PMS. No events shall be missed during an update procedure.
A latched bit is set when the associated event occurs, and remains set until it is cleared. Once cleared, a latched
bit will not be set again until the associated event reoccurs (goes away and comes back). A latched on change bit
is a latched bit that is set when the event occurs, and when it goes away. A latched status bit can be cleared using
clear on read or clear on write techniques, selectable by the
GL.CR1 .LSBCRE bit. When clear on write is selected,
the latched bits in a latched status register will be cleared after the register is read from. If the device is configured
for 16-bit mode, all 16 latched status bits will be cleared. If the device is configured for 8-bit mode, only the 8 bits
being accessed will be cleared. When clear on write is selected, the latched bits in a latched status register will be
cleared when a logic 1 is written to that bit position. For example, writing a FFFFh to a 16-bit latched status register
will clear any latched status bit, whereas writing a 0001h will only clear latched bit 0 of the latched status register.
Reserved bits and registers are implemented in a different mode. Reserved configuration bits and registers can be
written and read, however they will not affect the operation of the current mode. Reserved status bits will be zero.
Reserved latched status bits cannot be set, however, they may remain set or get set during a mode change.
Reserved interrupt enable bits can be written and read, and can cause an interrupt if the associated latched status
bit is set. Reserved counter registers and the associated counter will retain the values held before a mode change,
however, the associated counter cannot be incremented. A performance monitor update will operate normally. If
the data path reset is set during or after a mode change, the latched status bits and counter registers (with the
associated counters) will be automatically cleared. If the data path reset is not used, then the latched status bits
must be cleared via the register interface in the normal manner. And, the counter registers must be cleared by
performing two performance monitor updates. The first to clear the associated counter, and load the current count
into the counter register, and the second to clear the counter register.
The term “global” is used to make the register names compatible with the mult-port versions (DS3174, DS3173,
DS3172, DS3171) of this device.
NOTE: The RDY signal will not go active if the user attempts to read or write unused registers not assigned to any
design blocks. The RDY signal will go active if the user writes or reads reserved registers or unused registers within
design blocks.
Table 10-1. Register Address Map
Address
offset Description
000 - 01F Global registers
020 – 03F Unused
040 - 05F Port control registers
060 – 07F BERT
080 – 08B Unused