Rainbow Electronics DS3170 - Manual (Page 192)

DS3170 DS3/E3 Single-Chip Transceiver
192 of 233
1 = Transmit Frame Generation is disabled; E3 overhead positions in the incoming E3 payload will
be passed through to error insertion. Note: The E3 overhead periods can still be overwritten by by
error insertion, overhead insertion, or AIS generation.
Bit 0: Transmit Alarm Indication Signal (TAIS) – When 0, the normal signal is transmitted. When 1, the E3
output data stream is forced to all ones (AIS).
Register Name:
E3G832.TEIR
Register Description: E3 G.832 Transmit Error Insertion Register
Register Address: 11Ah
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- Reserved Reserved CFBEIE FBEI
Default 0 0 0 0 0 0 0 0
Bit
# 7 6 5 4 3 2 1 0
Name PBEE CPEIE PEI FEIC1 FEIC0 FEI TSEI MEIMS
Default
0 0 0 0 0 0 0 0
Bit 9: Continuous Remote Error Indication Error Insertion Enable (CFBEIE) – When 0, single remote error
indication (REI) error insertion is enabled. When 1, continuous REI error insertion is enabled, and REI errors will be
transmitted continuously if FBEI is high.
Bit 8: Remote Error Indication Error Insertion Enable (FBEI) – When 0, REI error insertion is disabled. When 1,
REI error insertion is enabled.
Bit 7: Parity Block Error Enable (PBEE) – When 0, a parity error is generated by inverting a single bit in the EM
byte. When 1, a parity error is generated by inverting all eight bits in the EM byte.
Bit 6: Continuous Parity Error Insertion Enable (CPEIE) – When 0, single parity (BIP-8) error insertion is
enabled. When 1, continuous parity error insertion is enabled, and parity errors will be transmitted continuously if
PEI is high.
Bit 5: Parity Error Insertion Enable (PEI) – When 0, parity error insertion is disabled. When 1, parity error
insertion is enabled.
Bits 4 to 3: Framing Error Control (FEIC[1:0]) – These two bits control the framing error event to be inserted.
00 = single bit error in one frame.
01 = word error in one frame.
10 = single bit error in four consecutive frames.
11 = word error in four consecutive frames.
Bit 2: Framing Error Insertion Enable (FEI) – When 0, framing error insertion is disabled. When 1, framing error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) – This bit causes an error of the enabled type(s) to be inserted in the
transmit data stream if manual error insertion is disabled (MEIMS = 0). A 0 to 1 transition causes a single error to
be inserted. For a second error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and
this bit transitions more than once between error insertion opportunities, only one error will be inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause an error to be inserted.