Transmit framer pin timing source selection – Rainbow Electronics DS3170 User Manual
Page 60
DS3170 DS3/E3 Single-Chip Transceiver
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9.2.3.1 Transmit Line Interface Pins Timing Source Selection
(TPOS/TDAT, TNEG)
The transmit line interface signal pin group has the same functional timing clock source as the TLCLK pin
described in
. Other clock pins can be used for the external timing. The TLCLK transmit line clock output
pin is always a valid output clock for external logic to use for these signals when
.TLTS=0.
The transmit line timing select bit (TLTS) is used to select input or output clock pin timing. When TLTS=0, output
clock timing is selected. When TLTS=1, input clock timing is selected. If TLTS is set for input clock timing and an
output clock pin is used, or if TLTS is set for output clock timing and an input clock pin is used, then the setup, hold
and delay timings, as specified in
will not be valid. There are some combinations of TLTS=1 and other
modes in which there is no input clock pin available for external timing since the clock source is derived internally
from the RX LIU or the CLAD.
Table 9-6. Transmit Line Interface Signal Pin Valid Timing Source Select
LOOP
T
LBM[2:0]
LIUEN
CLADC
TLTS
VALID TIMING TO THESE CLOCK PINS
1
XXX
X
X
0
TLCLK, TCLKO, RCLKO
1 XXX 0
X
1
RLCLK
1
XXX
1
X
1
No valid timing to any input clock pin
0
DLB (100)
X
X
0
TLCLK, TCLKO, RCLKO
0
LLB (010) or PLB (011)
X
X
0
TLCLK, RCLKO
0
DLB & LLB (110)
X
X
0
TLCLK
0
not DLB (100),
not LLB (010), not PLB (011)
and not LLB & DLB (110)
X
X
0
TLCLK, TCLKO (default)
0
not LLB (010) and not PLB (011)
and not LLB & DLB (110)
X
0
1
No valid timing to any input clock pin
0
not LLB (010) and not PLB (011)
and not LLB & DLB (110)
X 1 1
TCLKI
0
LLB (010) or PLB (011)
or DLB & LLB (110)
0 X 1
RLCLK
0
LLB (010) or PLB (011)
or DLB & LLB (110)
1
X
1
No valid timing to any input clock pin
9.2.3.2 Transmit Framer Pin Timing Source Selection
(TSER, TSOFI, TSOFO/TDEN)
The transmit framer signal pin group has the same functional timing clock source as the TCLKO pin described in
. Other clock pins can be used for the external timing. The TCLKO transmit clock output pin is always a
valid output clock for external logic to use for these signals when TFTS=0.
The transmit framer select bit (TFTS) is used to select input or output clock pin timing. When TFTS=0, output clock
timing is selected. When TFTS=1, input clock timing is selected. If TFTS is set for input clock timing and an output
clock pin is used, or If TFTS is set for output clock timing and an input clock pin is used, then the setup, hold and
delay timings, as specified in
, will not be valid. There are some combinations of TFTS=1 and other
modes in which there is no input clock pin available for external timing since the clock source is derived internally
from the RX LIU or the CLAD.