Port.sr, Port.isr – Rainbow Electronics DS3170 User Manual
Page 141
DS3170 DS3/E3 Single-Chip Transceiver
141 of 233
Register Name:
PORT.ISR
Register Description:
Port Interrupt Status Register
Register Address:
050h
Bit
# 15 14 13 12 11 10 9 8
Name
-- -- -- -- -- --
PSR
LCSR
Bit
# 7 6 5 4 3 2 1 0
Name TTSR FSR HSR BSR
RESERVED
RESERVED
RESERVED
FMSR
Bit 9: Port Status Register Interrupt Status (PSR) This bit is set when any of the latched status register bits, that
are enabled for interrupt, in the PORT.SRL register are set. The interrupt pin will be driven when this bit is set and
the
.PISRIE bit is set.
Bit 8: Line Code Status Register Interrupt Status (LCSR) This bit is set when any of the latched status register
bits, that are enabled for interrupt, in the B3ZS/HDB3 Line Encoder/Decoder block are set. The interrupt pin will be
driven when this bit is set and the
.PISRIE bit is set.
Bit 7: Trail Trace Status Register Interrupt Status (TTSR) This bit is set when any of the latched status register
bits, that are enabled for interrupt, in the trail trace block are set. The interrupt pin will be driven when this bit is set
and the
.PISRIE bit is set.
Bit 6: FEAC Status Register Interrupt Status (FSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the FEAC block are set. The interrupt pin will be driven when this bit is set and the
.PISRIE bit is set.
Bit 5: HDLC Status Register Interrupt Status (HSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the HDLC block are set. The interrupt pin will be driven when this bit is set and the
.PISRIE bit is set.
Bit 4: BERT Status Register Interrupt Status (BSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the BERT block are set. The interrupt pin will be driven when this bit is set and the
.PISRIE bit is set.
Bit 0: Framer Status Register Interrupt Status (FMSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the active DS3 or E3 framer block are set. The interrupt pin will be driven when this
bit is set and the
.PISRIE bit is set.
Register Name:
PORT.SR
Register Description:
Port Status Register
Register Address:
052h
Bit
# 15 14 13 12 11 10 9 8
Name
-- -- -- -- -- -- -- --
Bit
# 7 6 5 4 3 2 1 0
Name
-- -- -- -- --
TDM RLOL PMS
Bit 2: Transmit Driver Monitor Status (TDM) This bits indicates the status of the transmit monitor circuit in the
transmit LIU.
0 = Transmit output not over loaded
1 = Transmit signal is overloaded